View MVME1603_935080.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MVME1603/mvme1604 single board computer installation and use v1600-1a/ih4 .com .com .com .com 4 .com u datasheet
notice while reasonable efforts have been made to assure the accuracy of this document, motorola, inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of motorola to notify any person of such revision or changes. no part of this material may be reproduced or copied in any tangible medium, or stored in a retrieval system, or transmitted in any form, or by any means, radio, electronic, mechanical, photocopying, recording or facsimile, or otherwise, without the prior written permission of motorola, inc. it is possible that this publication may contain reference to, or information about motorola products (machines and programs), programming, or services that are not announced in your country. such references or information must not be construed to mean that motorola intends to announce such motorola products, programming, or services in your country. restricted rights legend if the documentation contained herein is supplied, directly or indirectly, to the u.s. government, the following notice shall apply unless otherwise agreed to in writing by motorola, inc. use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the rights in technical data and computer software clause at dfars 252.227-7013. motorola, inc. computer group 2900 south diablo way tempe, arizona 85282 .com .com .com .com .com 4 .com u datasheet
preface the MVME1603/mvme1604 single board computer installation and use manual provides general product information along with hardware preparation, installation, and operating instructions. a functional description and various types of interfacing information for the MVME1603/mvme1604 family of single board computers is also included. this manual is intended for anyone who wants to design oem systems, supply additional capability to an existing compatible system, or work in a lab environment for experimental purposes. a basic knowledge of computers and digital logic is assumed. to use this manual, you should be familiar with the publications listed in appendix a of this manual. the MVME1603/1604 family of single board computers has two parallel branches based on two distinct versions of the base board. both versions are populated with a number of similar plug-together components, which are listed in the following table.. base board processor module dram transition module mvme1600-001 pm603-00 x pm604-00 x pm604-01 x ram104-00 x mvme760 pm603-01 x pm603-02 x pm603-03 x mvme1600-011 pm603-00 x pm604-00 x pm604-01 x ram104-00 x mvme712m pm603-01 x pm603-02 x pm603-03 x .com .com .com .com .com 4 .com u datasheet
throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric format as follows: $ dollar specifies a hexadecimal character % percent specifies a binary number & ampersand specifies a decimal number unless otherwise specified, all address references are in hexadecimal. an asterisk (*) following the signal name for signals which are level-significant denotes that the signal is true or valid when the signal is low. an asterisk (*) following the signal name for signals which are edge-significant denotes that the actions initiated by that signal occur on high-to-low transition. in this manual, assertion and negation are used to specify forcing a signal to a particular state. in particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. these terms are used independently of the voltage level (high or low) that they represent. data and address sizes are defined as follows: a byte is eight bits, numbered 0 through 7, with bit 0 being the least significant. a half word is 16 bits, numbered 0 through 15, with bit 0 being the least significant. a word is 32 bits, numbered 0 through 31, with bit 0 being the least significant. a double word is 64 bits, numbered 0 through 63, with bit 0 being the least significant. motorola ? and the motorola symbol are registered trademarks of motorola, inc. aix? is a trademark of ibm corp. powerpc? is a trademark of ibm corp. and is used by motorola with permission. all other products mentioned in this document are trademarks or registered trademarks of their respective holders. ? copyright motorola 1999 all rights reserved printed in the united states of america march 1999 .com .com .com .com .com 4 .com u datasheet
safety summary safety depends on you the following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. motorola, inc. assumes no liability for the customer's failure to comply with these requirements. the safety precautions listed below represent warnings of certain dangers of which motorola is aware. you, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment. ground the instrument. to minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. the equipment is supplied with a three-conductor ac power cable. the power cable must be plugged into an approved three-contact electrical outlet. the power jack and mating plug of the power cable meet international electrotechnical commission (iec) safety standards. do not operate in an explosive atmosphere. do not operate the equipment in the presence of flammable gases or fumes. operation of any electrical equipment in such an environment constitutes a definite safety hazard. keep away from live circuits. operating personnel must not remove equipment covers. only factory authorized service personnel or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment. do not replace components with power cable connected. under certain conditions, dangerous voltages may exist even with the power cable removed. to avoid injuries, always disconnect power and discharge circuits before touching them. do not service or adjust alone. do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present. use caution when exposing or handling the crt. breakage of the cathode-ray tube (crt) causes a high-velocity scattering of glass fragments (implosion). to prevent crt implosion, avoid rough handling or jarring of the equipment. handling of the crt should be done only by qualified maintenance personnel using approved safety mask and gloves. do not substitute parts or modify equipment. because of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modification of the equipment. contact your local motorola representative for service and repair to ensure that safety features are maintained. dangerous procedure warnings. warnings, such as the example below, precede potentially dangerous procedures throughout this manual. instructions contained in the warnings must be followed. you should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment. ! warning dangerous voltages, capable of causing death, are present in this equipment. use extreme caution when handling, testing, and adjusting. .com .com .com .com .com 4 .com u datasheet
all motorola pwbs (printed wiring boards) are manufactured by ul-recognized manufacturers, with a flammability rating of 94v-0. ! warning this equipment generates, uses, and can radiate electro- magnetic energy. it may cause or be susceptible to electro- magnetic interference (emi) if not installed and used in a cabinet with adequate emi protection. european notice: board products with the ce marking comply with the emc directive (89/336/eec). marking a system with the ce symbol indicates compliance of that motorola system to the applicable directives of the european community. a system with the ce marking meets or exceeds the following technical standards: en55022 (cispr 22): limits and methods of measurement of radio interference characteristics of information technology equipment. tested to equipment class b. en50082-1, 1992: electromagnetic compatibility -- generic immunity standard, part 1: residential, commercial and light industry. iec801-2: electromagnetic compatibility for industrial process measurement and control equipment, part 2: electrostatic discharge requirements. iec801-3: electromagnetic compatibility for industrial process measurement and control equipment, part 3: radiated electromagnetic field requirements. iec801-4: electromagnetic compatibility for industrial process measurement and control equipment, part 4: electrical fast transient/burst requirements. the product also fulfills en60950 (product safety) which is essentially the requirement for the low voltage directive (73/23/eec). in accordance with european community directives, a declaration of conformity has been made and is on file at motorola, inc. - computer group, 27 market street, maidenhead, united kingdom, sl6 8ae. this board product was tested in a representative system to show compliance with the above mentioned requirements. a proper installation in a ce -marked system will maintain the required emc/safety performance. .com .com .com .com .com 4 .com u datasheet
vii contents chapter 1 hardware preparation and installation introduction................................................................................................................1-1 equipment required ..................................................................................................1-2 overview of startup procedure..................................................................................1-5 unpacking instructions ..............................................................................................1-6 hardware configuration ............................................................................................1-6 mvme1600-001 base board preparation.................................................................1-7 scsi bus terminator selection (j7) ...................................................................1-7 general-purpose software-readable header (j8) ..............................................1-8 console port configuration ................................................................................1-9 vmebus system controller selection (j9).......................................................1-10 serial port 3 clock configuration (j10) ...........................................................1-11 serial port 4 clock configuration (j13) ...........................................................1-13 remote status and control ...............................................................................1-13 mvme760 transition module preparation .............................................................1-14 configuration of serial ports 3 and 4 ...............................................................1-15 mvme1600-011 base board preparation ...............................................................1-18 serial port 4 dce/dte selection (j7) .............................................................1-18 serial port 4 clock selection (j8/15/16)...........................................................1-20 serial port 4 i/o path selection (j9).................................................................1-21 vmebus system controller selection (j10).....................................................1-22 serial port 3 i/o path selection (j13)...............................................................1-23 general-purpose software-readable header (j14) ..........................................1-23 remote status and control ...............................................................................1-25 mvme712m transition module preparation .........................................................1-27 serial ports 1-4 dce/dte configuration ........................................................1-29 serial port 4 clock configuration ....................................................................1-29 hardware installation...............................................................................................1-32 esd precautions ...............................................................................................1-32 pm603/604 processor/memory mezzanine.............................................................1-33 ram104 memory mezzanine installation ..............................................................1-35 MVME1603/1604 vmemodule installation ...........................................................1-38 mvme760 transition module installation .............................................................1-39 mvme712m transition module installation..........................................................1-42 system considerations.............................................................................................1-45 mvme1600-001 base board ...........................................................................1-46 mvme1600-011 base board ...........................................................................1-47 .com .com .com .com .com 4 .com u datasheet
viii chapter 2 operating instructions introduction ............................................................................................................... 2-1 applying power......................................................................................................... 2-1 abort switch (s1)........................................................................................... 2-1 reset switch (s2)............................................................................................ 2-2 front panel indicators (ds1 - ds6) ................................................................... 2-3 memory maps............................................................................................................ 2-4 mpu bus memory map ..................................................................................... 2-4 normal address range ............................................................................... 2-4 pci local bus memory map ............................................................................. 2-9 vmebus memory map .................................................................................... 2-10 programming considerations .................................................................................. 2-17 pci arbitration ................................................................................................. 2-18 interrupt handling ............................................................................................ 2-20 machine check interrupt (mcp*) ............................................................ 2-21 maskable interrupts................................................................................... 2-21 vmechip2 interrupts ................................................................................ 2-23 z8536 and z85230 interrupts.................................................................... 2-23 dma channels................................................................................................. 2-24 sources of reset ............................................................................................... 2-24 endian issues .................................................................................................... 2-25 processor/memory domain ...................................................................... 2-25 pci domain............................................................................................... 2-28 vmebus domain ...................................................................................... 2-28 chapter 3 functional description introduction ............................................................................................................... 3-1 features...................................................................................................................... 3 -1 general description................................................................................................... 3-3 block diagram........................................................................................................... 3-4 scsi interface .................................................................................................... 3-6 scsi termination........................................................................................ 3-6 ethernet interface ............................................................................................... 3-7 graphics interface .............................................................................................. 3-8 pci mezzanine interface .................................................................................... 3-9 vmebus interface ............................................................................................ 3-10 isa super i/o device (isasio) ...................................................................... 3-10 asynchronous serial ports ........................................................................ 3-10 parallel port ............................................................................................... 3-11 disk drive controller................................................................................ 3-12 .com .com .com .com .com 4 .com u datasheet
ix keyboard and mouse interface..................................................................3-12 isa bridge controller.......................................................................................3-12 real-time clock and nvram ........................................................................3-13 programmable timers.......................................................................................3-14 interval timers ..........................................................................................3-14 16-bit timers.............................................................................................3-15 vmechip2 timers .....................................................................................3-15 serial communications interface......................................................................3-15 z8536 cio device.....................................................................................3-16 board configuration register...........................................................................3-16 p2 signal multiplexing .....................................................................................3-17 abort switch (s1) .........................................................................................3-19 reset switch (s2) ..........................................................................................3-20 front panel indicators (ds1 - ds6)..................................................................3-21 polyswitches (resettable fuses).......................................................................3-22 mvme1600-001 base board....................................................................3-22 mvme1600-011 base board....................................................................3-23 speaker control ................................................................................................3-24 pm603/604 processor/memory mezzanine module ........................................3-24 ram104 memory module ...............................................................................3-26 mvme760 transition module .........................................................................3-27 serial interface modules............................................................................3-27 mvme712m transition module......................................................................3-28 chapter 4 connector pin assignments common connectors .................................................................................................4-2 led mezzanine connector ................................................................................4-3 mpu mezzanine connector................................................................................4-3 cpu connector ...................................................................................................4-6 dram expansion connectors .........................................................................4-10 pci mezzanine card connectors......................................................................4-11 vmebus connector p1 .....................................................................................4-11 ethernet 10baset connector ............................................................................4-14 disk drive connector .......................................................................................4-15 mvme1600-001 connectors...................................................................................4-16 vmebus connector p2 .....................................................................................4-16 scsi connector ................................................................................................4-16 graphics connector ..........................................................................................4-18 keyboard and mouse connectors.....................................................................4-19 ethernet aui connector ...................................................................................4-20 .com .com .com .com .com 4 .com u datasheet
x parallel i/o connector...................................................................................... 4-21 serial ports 1 and 2........................................................................................... 4-22 serial ports 3 and 4........................................................................................... 4-23 mvme1600-011 connectors .................................................................................. 4-24 vmebus connector p2..................................................................................... 4-24 scsi connector................................................................................................ 4-24 ethernet aui connector................................................................................... 4-27 parallel i/o connector...................................................................................... 4-28 serial ports 1-4 ................................................................................................. 4-29 chapter 5 ppcbug overview ................................................................................................................... 5-1 memory requirements ....................................................................................... 5-2 ppcbug implementation .................................................................................... 5-2 using the debugger ................................................................................................... 5-3 debugger commands ......................................................................................... 5-4 diagnostic tests.................................................................................................. 5-7 chapter 6 cnfg and env commands overview ................................................................................................................... 6-1 cnfg - configure board information block............................................................ 6-2 env - set environment............................................................................................. 6-3 configuring the ppcbug parameters ................................................................. 6-3 configuring the vmebus interface .................................................................. 6-12 slave address decoders............................................................................ 6-13 appendix a related documentation motorola computer group documents .................................................................... a-1 manufacturers documents ...................................................................................... a-3 related specifications .............................................................................................. a-8 appendix b specifications specifications............................................................................................................ b-1 cooling requirements .............................................................................................. b-2 emc compliance ..................................................................................................... b-3 .com .com .com .com .com 4 .com u datasheet
xi appendix c serial interconnections introduction............................................................................................................... c-1 asynchronous serial ports................................................................................. c-1 synchronous serial ports ................................................................................... c-2 eia-232-d connections ........................................................................................... c-3 interface characteristics .................................................................................... c-4 eia-530 connections................................................................................................ c-5 interface characteristics .................................................................................... c-8 proper grounding...................................................................................................... c-9 appendix d troubleshooting cpu boards: solving startup problems introduction...............................................................................................................d-1 glossary abbreviations, acronyms, and terms to know..................................................... gl-1 figures figure 1-1. mvme1600-001 base board block diagram ........................................1-3 figure 1-2. mvme1600-011 base board block diagram ........................................1-4 figure 1-3. mvme1600-001 switches, headers, connectors, fuses, leds..........1-12 figure 1-4. mvme760 connector and header locations.......................................1-17 figure 1-5. mvme1600-011 switches, headers, connectors, fuses, leds ..........1-19 figure 1-6. mvme712m connector and header locations ...................................1-28 figure 1-7. j15 clock line configuration ...............................................................1-29 figure 1-8. mvme1600-011 serial port 4 clock configuration ............................1-30 figure 1-9. p2 adapter component placement .......................................................1-31 figure 1-10. pm603/pm604 placement on MVME1603/1604 ...............................1-34 figure 1-11. ram104 placement on pm603/pm604..............................................1-36 figure 1-12. mvme760/mvme1600-001 cable connections ..............................1-41 figure 1-13. mvme712m/mvme1600-011 cable connections...........................1-44 figure 2-1. ibc arbiter configuration diagram .....................................................2-19 figure 2-2. MVME1603/mvme1604 interrupt architecture.................................2-20 figure 2-3. ibc interrupt handler block diagram..................................................2-22 figure 2-4. big-endian mode ..................................................................................2-26 figure 2-5. little-endian mode ...............................................................................2-27 figure 3-1. MVME1603/mvme1604 block diagram .............................................3-5 .com .com .com .com .com 4 .com u datasheet
xii tables table 1-1. startup overview...................................................................................... 1-5 table 1-2. remote reset connector j1 interconnect signals.................................. 1-14 table 1-3. remote reset connector j4 interconnect signals.................................. 1-26 table 2-1. processor view of the memory map........................................................ 2-5 table 2-2. pci configuration space memory map................................................... 2-6 table 2-3. isa/pci i/o space memory map ........................................................... 2-7 table 2-4. pci view of the memory map ................................................................. 2-9 table 2-5. vme2pci view of the memory map .................................................... 2-11 table 2-6. vmechip2 memory map (sheet 1 of 3) ................................................ 2-12 table 2-6. vmechip2 memory map (sheet 2 of 3) ................................................ 2-14 table 2-6. vmechip2 memory map (sheet 3 of 3) ................................................ 2-17 table 2-7. pci arbitration assignments ................................................................. 2-19 table 2-8. ibc dma channel assignments ........................................................... 2-24 table 3-1. MVME1603/mvme1604 features ........................................................ 3-1 table 3-2. p2 multiplexing sequence ..................................................................... 3-18 table 3-3. fuse assignments by base board .......................................................... 3-22 table 3-4. minimum romfal and romnal values .......................................... 3-26 table 3-5. module type identification .................................................................... 3-27 table 4-1. led mezzanine connector ...................................................................... 4-3 table 4-2. mpu mezzanine connector .................................................................... 4-4 table 4-3. cpu connector ........................................................................................ 4-7 table 4-4. dram mezzanineconnector 1.......................................................... 4-10 table 4-5. dram mezzanineconnector 2.......................................................... 4-11 table 4-6. pci mezzanine card connector............................................................. 4-12 table 4-7. vmebus connector p1........................................................................... 4-13 table 4-8. ethernet 10baset connector.................................................................. 4-14 table 4-9. disk drive mezzanine connector .......................................................... 4-15 table 4-10. scsi connector .................................................................................... 4-17 table 4-11. graphics connector .............................................................................. 4-18 table 4-12. keyboard connector............................................................................. 4-19 table 4-13. mouse connector ................................................................................. 4-19 table 4-14. ethernet aui connector (mvme760)................................................. 4-20 table 4-15. parallel i/o connector (mvme760).................................................... 4-21 table 4-16. serial connectionsports 1 and 2 (mvme760)................................. 4-22 table 4-17. serial connectionsports 3 and 4 (mvme760)................................. 4-23 table 4-18. vmebus connector p2......................................................................... 4-25 table 4-19. scsi connector (mvme712m) .......................................................... 4-26 .com .com .com .com .com 4 .com u datasheet
xiii table 4-20. ethernet aui connector (mvme712m) .............................................4-27 table 4-21. parallel i/o connector (mvme712m).................................................4-28 table 4-22. serial connectionsmvme712m ports 1-4.......................................4-29 table 4-23. serial connectionsmvme1600-011 ports 3 and 4 ..........................4-30 table 5-1. debugger commands ..............................................................................5-4 table 5-2. diagnostic test groups.............................................................................5-7 table a-1. motorola computer group documents .................................................a-2 table a-2. manufacturers documents ..................................................................a-3 table a-3. related specifications ..........................................................................a-8 table b-1. mvme1600-001/mvme1600-011 specifications ............................... b-1 table c-1. mvme1600-001/mvme1600-011 serial ports ................................... c-1 table c-2. eia-232-d interconnect signals ........................................................... c-3 table c-3. eia-232-d interface transmitter characteristics .................................. c-5 table c-4. eia-232-d interface receiver characteristics ...................................... c-5 table c-5. mvme760 eia-530 interconnect signals ........................................... c-6 table c-6. eia-530 interface transmitter characteristics ...................................... c-8 table c-7. eia-530 interface receiver characteristics .......................................... c-9 table d-1. basic troubleshooting steps for all cpu boards .............................d-1 table d-2. troubleshooting MVME1603/mvme1604 boards ............................d-3 .com .com .com .com .com 4 .com u datasheet
xiv .com .com .com .com .com 4 .com u datasheet
1 1-1 1 hardware preparation and installation introduction this manual provides general product information along with hardware preparation, installation and operating instructions for the MVME1603/1604 family of single board computers. the MVME1603/1604 is a double-high vmemodule equipped with a powerpc? series microprocessor. the MVME1603 is equipped with a powerpc 603 microprocessor; the mvme1604 has a powerpc 604 microprocessor. 256kb of level 2 (l2) cache memory is available as an option on both versions. the MVME1603/1604 family has two parallel branches based on two distinct versions (mvme1600-001 and mvme1600-011) of the base board. the differences between the mvme1600-001 and the mvme1600-011 lie mainly in the area of i/o handling; the logic design is the same for both versions. in either case, the complete MVME1603/1604 consists of the base board plus: o a processor/memory module (pm603 or pm604) with optional l2 cache o an led mezzanine (mezled) to supply status indicators and reset/abort switches o a dram module (ram104) for additional memory o an optional pci mezzanine card (pmc) for additional versatility the block diagrams in figures 1-1 and 1-2 illustrate the architecture of the mvme1600-001 and the mvme1600-011 base boards. .com .com .com .com .com 4 .com u datasheet
equipment required 1-2 1 equipment required the following equipment is required to complete an MVME1603/ 1604 system: o vme system enclosure o system console terminal o transition module (mvme760 for the mvme1600-001 base boards, mvme712m for the mvme1600-011) and connecting cables o disk drives (and/or other i/o) and controllers o operating system (and/or application software) .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-3 1 figure 1-1. mvme1600-001 base board block diagram kbd mouse db15 68-pin connector terminators graphics cl-gd5446 dram 256kx16 scsi ncr-53c825 pci local bus isa bus s82378zb isa bridge ethernet decchip vme2pci bridge to mpu module pmc slot aui 10bt vme vmechip2 decode function pc87303 super i/o rtc mk48t18 escc 85230 cio z8536 p2mx function p2 connector p1 connector buffers parallel com1 com2 21040 .com .com .com .com .com 4 .com u datasheet
equipment required 1-4 1 figure 1-2. mvme1600-011 base board block diagram 11199.00 9502 hd26 escc 85230 hd26 to mpu module 10bt pmc slot eia232 rj45 aui buffers p1 connector p2 connector pci local bus isa bus cio z8536 s82378zb isa bridge scsi ncr-53c810 ethernet decchip vme2pci bridge pc87303 super i/o rtc mk48t18 csrs vme vmechip2 parallel com1 com2 serial 4 serial3 21040 .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-5 1 overview of startup procedure the following table lists the things you will need to do before you can use this board and tells you where to find the information that you need to perform each step. please read this entire chapter, including all caution and warning notes, before you begin. table 1-1. startup overview what you need to do... refer to... on page... unpack the hardware. unpacking instructions 1-6 configure the hardware by setting jumpers on the boards and transition modules. mvme1600-001 base board preparation and mvme760 transition module preparation 1-7 and 1-15 mvme1600-011 base board preparation and mvme712m transition module preparation 1-18 and 1-27 ensure processor and memory mezzanines are properly installed on the base board. pm60x processor/memory mezzanine installation and ram104 memory mezzanine installation 1-33 and 1-35 install the MVME1603/1604 vmemodule in the chassis. MVME1603/1604 vmemodule installation 1-37 install the transition module in the chassis. mvme760 transition module installation or mvme712m transition module installation 1-39 or 1-42 connect a console terminal. console port configuration 1-9 connect any other equipment you will be using. connector pin assignments 4-1 for more information on optional devices and equipment, refer to the documentation provided with the equipment. power up the system. switches and leds 2-1 troubleshooting the MVME1603/1604; solving start-up problems d-1 note that the debugger prompt appears. using the debugger 5-3 you may also wish to obtain the ppcbug firmware package users manual listed in appendix a. a-1 initialize the clock. debugger commands , set time and date ( set )5-6 examine and/or change environmental parameters. cnfg and env commands 6-1 program the board as needed for your applications. MVME1603/1604 programmers reference guide listed in appendix a. a-1 .com .com .com .com .com 4 .com u datasheet
unpacking instructions 1-6 1 unpacking instructions note if the shipping carton is damaged upon receipt, request that the carrier's agent be present during the unpacking and inspection of the equipment. unpack the equipment from the shipping carton. refer to the packing list and verify that all items are present. save the packing material for storing and reshipping of equipment. ! caution avoid touching areas of integrated circuitry; static discharge can damage circuits. hardware configuration to produce the desired configuration and ensure proper operation of the MVME1603/1604, you may need to carry out certain modifications before installing the module. the MVME1603/1604 provides software control over most options: by setting bits in control registers after installing the MVME1603/ 1604 in a system, you can modify its configuration. (the MVME1603/1604 control registers are described in chapter 3, and/or in the MVME1603/mvme1604 single board computer programmer's reference guide as listed under related documentation in appendix a.) some options, however, are not software-programmable. such options are controlled through manual installation or removal of header jumpers or interface modules on the base board or the associated modules. .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-7 1 mvme1600-001 base board preparation figure 1-3 illustrates the placement of the switches, jumper headers, connectors, and led indicators on the mvme1600-001. manually configurable items on the base board include: o scsi bus terminator selection (j7) o general-purpose software-readable header (j8) o vmebus system controller selection (j9) o serial port 3 clock configuration (j10) o serial port 4 clock configuration (j13) serial ports on the associated mvme760 transition module are also manually configurable. for a discussion of the configurable items on the transition module, refer to the users manual for the mvme760 (part number vme760ua) as necessary. the mvme1600-001 has been factory tested and is shipped with the configurations described in the following sections. the mvme1600- 001s required and factory-installed debug monitor, ppcbug, operates with those factory settings. scsi bus terminator selection (j7) the mvme1600-001 provides terminators for the scsi bus. the scsi terminators are enabled or disabled by a jumper on header j7. the scsi terminators may be configured as follows. j7 on-board scsi bus termination enabled j7 (factory configuration) on-board scsi bus termination disabled 1 2 1 2 .com .com .com .com .com 4 .com u datasheet
mvme1600-001 base board preparation 1-8 1 general-purpose software-readable header (j8) header j8 provides eight readable jumpers. these jumpers can be read as a register at isa i/o address $80000801. bit 0 is associated with header pins 1 and 2; bit 7 is associated with pins 15 and 16. the bit values are read as a zero when the jumper is installed, and as a one when the jumper is removed. the powerpc firmware (ppcbug) reserves the four lower-order bits, srh3 to srh0. they are defined as shown in the list below: the four higher-order bits, srh4 to srh7, are user-definable. they can be allocated as necessary to specific applications. the mvme1600-001 is shipped from the factory with j8 set to all zeros (jumpers on all pins). low-order bit pins definition bit #0 (srh0) 12 reserved for future use. bit #1 (srh1) 34 with the jumper installed between pins 3 and 4 (factory configuration), the debugger uses the current user setup/operation parameters in nvram. when the jumper is removed (making the bit a 1 ), the debugger uses the default setup/operation parameters in rom instead. refer to the env command description in chapter 6 for the rom defaults. bit #2 (srh2) 56 reserved for future use. bit #3 (srh3) 78 reserved for future use. j8 2 srh7 srh6 srh5 srh1 srh4 srh3 srh2 16 15 1 srh0 user-definable user-definable user-definable setup parameter source (in=nvram; out=rom) user-definable reserved for future use reserved for future use reserved for future use ppcbug installed 87 .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-9 1 console port configuration on the mvme1600-001 base board, either the standard serial console port ( com1 ) or the on-board video (vga) port can serve as the ppcbug firmware console port. the firmware checks for the presence of a connected keyboard and a connected mouse. if either device is connected to the powerpc system and a firmware-supported video card/video device is found, the firmware is automatically brought up on the connected video terminal. if neither a mouse nor keyboard is connected, the firmware is brought up on the serial port ( com1 ). it is also brought up on the serial port ( com1 ) if no video terminal is found. the following table shows how the display device is determined: notes if the mouse is connected but the keyboard is not, and the supported vga device exists, the firmware is displayed on the video terminal. because a keyboard is necessary for interactive use on a video terminal, however, the firmware will display a keyboard not connected message. in order to use the firmware, you must then plug the keyboard in. conversely, if you remove the vga monitor, also remove the keyboard and mouse to avoid unexpected behavior by the firmware. mouse con- nected keyboard connected on-board vga device present firmware displayed on yes yes yes vga terminal yes no yes vga terminal no yes yes vga terminal no no yes serial port ( com1 ) no no no serial port ( com1 ) no yes no serial port ( com1 ) .com .com .com .com .com 4 .com u datasheet
mvme1600-001 base board preparation 1-10 1 if you plan to use a terminal other than a vga device as the firmware console, set it up as follows: o eight bits per character o one stop bit per character o parity disabled (no parity) o baud rate of 9600 baud 9600 baud is the power-up default for serial ports on MVME1603/ 1604 boards. after power-up you can reconfigure the baud rate if you wish, via the ppcbug firmwares port format ( pf ) command. whatever the baud rate, the terminal must perform some type of hardware handshaking either xon/off or via the cts line. vmebus system controller selection (j9) the mvme1600-001 is factory-configured in system controller mode (i.e., a jumper is installed across pins 2 and 3 of header j9). this means that the mvme1600-001 assumes the role of system controller at system power-up or reset. leave the jumper installed across pins 2 and 3 if you intend to operate the mvme1600-001 as system controller in all cases. remove the jumper from j9 if the mvme1600-001 is not to operate as system controller under any circumstances. note that when the mvme1600-001 is functioning as system controller, the sys led is turned on. 1 2 3 j9 not system controller 1 2 3 j9 system controller (factory configuration) .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-11 1 serial port 3 clock configuration (j10) you can configure serial port 3 on the mvme1600-001 to use the clock signals provided by the txc signal line. header j10 configures port 3 to either drive or receive txc. the factory configuration has port 3 set to receive txc. to complete the configuration of the txc clock line, you must also set serial port 3 clock configuration header j9 on the mvme760 transition module, described later in this chapter. for details on the configuration of that header, refer to the mvme760 transition module section or to the users manual for the mvme760 (part number vme760ua). receive txc drive txc (factory configuration) 321 j10 321 j10 .com .com .com .com .com 4 .com u datasheet
mvme1600-001 base board preparation 1-12 1 figure 1-3. mvme1600-001 switches, headers, connectors, fuses, leds p1 a1 b1 c1 a32 b32 c32 p2 a32 b32 c32 a1 b1 c1 j2 2 1 152 151 2 1 j14 j12 j13 2 1 3 33 34 1 2 j6 36 35 34 33 68 67 64 63 1 3 1 1 3 j10 j9 j8 16 15 21 2 1 j7 65 43 j5 65 43 j4 51 10 j3 6 15 11 j1 14 2 113 f1 f2 f3 f4 j11 2 1 64 63 11195.00 9502 (2-3) mvme 1600-001 abt pci mezzanine card rst monitor keyboard mouse scsi chs bfl cpu pci fus sys 1 4 1 j15 j16 2 .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-13 1 serial port 4 clock configuration (j13) you can configure serial port 4 on the mvme1600-001 to use the clock signals provided by the txc signal line. header j13 configures port 4 to either drive or receive txc. the factory configuration has port 4 set to receive txc. to complete the configuration of the txc clock line, you must also set serial port 4 clock configuration header j8 on the mvme760 transition module (described later in this chapter). for details on the configuration of that header, refer to the mvme760 transition module section or to the users manual for the mvme760 (part number vme760ua). remote status and control the mvme1600-001 front panel leds and switches are mounted on a removable mezzanine board. removing the led mezzanine makes the mezzanine connector (j1, a keyed double-row 14-pin connector) available for service as a remote status and control connector. this allows a system designer to construct a reset/led panel that can be located apart from the mvme1600-001. maximum cable length is 15 feet. in this application, j1 can be connected to a user-supplied external cable to carry the signals for remote reset, abort, the leds, and a general-purpose i/o signal. the i/o signal is a general-purpose interrupt pin which can also function as a trigger input. the interrupt pin is level programmable. table 1-2 lists the pin numbers, signal mnemonics, and signal descriptions for j1. receive txc drive txc 3 2 1 j13 3 2 1 j13 (factory configuration) .com .com .com .com .com 4 .com u datasheet
mvme760 transition module preparation 1-14 1 mvme760 transition module preparation the mvme760 transition module (figure 1-4) is used in conjunction with the mvme1600-001 base board. the features of the mvme760 include: o a parallel printer port table 1-2. remote reset connector j1 interconnect signals pin number signal mnemonic signal name and description 1 not used . 2 resetsw * reset switch . signal goes low when the reset switch is pressed. it may be forced low externally for a remote reset. 3 irq interrupt request . general-purpose interrupt input line. 4abortsw * abort switch . signal goes low when the abort switch is pressed. it may be forced low externally for a remote abort. 5 pciled * pci led . signal goes low when the pci led illuminates. 6 failled * fail led . signal goes low when the fail led illuminates. 7 lanled * lan led . signal goes low when the lan led illuminates. 8 statled * status led . signal goes low when the status led illuminates. 9 fuseled * rpwr led . signal goes low when the fuse led illuminates. 10 runled * run led . signal goes low when the run led illuminates. 11 scsiled * scsi led . signal goes low when the scsi led illuminates. 12 sconled * scon led . signal goes low when the scon led illuminates. 13 +5vrmt +5 vdc power . fused through fuse f1; +5 vdc power to a user-supplied external connection. 14 spkr speaker . speaker output line. .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-15 1 o an ethernet interface supporting both aui and 10baset connections o two eia-232-d asynchronous serial ports (identified as com1 and com2 on the front panel) o two synchronous serial ports (ports 3 and 4) configuration of serial ports 3 and 4 the synchronous serial ports, serial port 3 and serial port 4, are configurable via a combination of serial interface modules (sims) and jumper settings. the following table lists the synchronous serial ports with their corresponding sim connectors and jumper headers. port 3 is routed both to board connector j7 and to the hd26 front panel connector marked serial 3 . port 4 is available only at board connector j2. four serial interface modules are available: o eia-232-d (dce and dte) o eia-530 (dce and dte) you can change serial ports 3 and 4 from an eia-232-d to an eia-530 interface (or vice-versa) by mounting the appropriate sim705 series interface module and setting the corresponding jumper. sims can be ordered separately as required. synchronous port board connector panel connector sim connector jumper header port 3 j7 serial 3 j6 j9 port 4 j2 none j4 j8 .com .com .com .com .com 4 .com u datasheet
mvme760 transition module preparation 1-16 1 headers j9 and j8 are used to configure serial port 3 and serial port 4, respectively. with the jumper in position 1-2, the port is configured as a dte. with the jumper in position 2-3, the port is configured as a dce. the jumper setting of the port should match the configuration of the corresponding sim module . when installing the sim modules, note that the headers are keyed for proper orientation. for further information on the preparation of the transition module, refer to the users manual for the mvme760 (part number vme760a/um) as necessary. 321 j8 321 j8 321 j9 321 j9 serial port 3 jumper settings dte dce serial port 4 jumper settings dte dce .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-17 1 figure 1-4. mvme760 connector and header locations mvme 760-001 serial 3 ethernet com1 com2 parallel 10baset 1551 9410 25 26 j2 1 2 60 59 2 1 j4 p2 a32 b32 c32 a1 b1 c1 15 96 j1 15 96 j3 13 1 25 15 j5 2 17 1 36 20 j10 2 81 15 9 j11 2 28 17 60 59 2 1 j6 25 26 j7 1 2 j12 j8 j9 31 31 f1 .com .com .com .com .com 4 .com u datasheet
mvme1600-011 base board preparation 1-18 1 mvme1600-011 base board preparation figure 1-5 illustrates the placement of the switches, jumper headers, connectors, and led indicators on the mvme1600-011. manually configurable items on the base board include: o serial port 4 dce/dte selection (j7) o serial port 4 clock selection (j8, j15, j16) o serial port 4 i/o path selection (j9) o vmebus system controller selection (j10) o serial port 3 i/o path selection (j13) o general-purpose software-readable header (j14) serial ports on the associated mvme712m transition module are also manually configurable. for a discussion of the configurable items on the transition module, refer to the users manual for the mvme712m (part number mvme712m) as necessary. the mvme1600-011 has been factory tested and is shipped with the configurations described in the following sections. the required and factory-installed debug monitor, ppcbug, operates with those factory settings. serial port 4 dce/dte selection (j7) serial port 4 on the mvme1600-011 is dce/dte configurable. header j7 sets a configuration bit for serial port 4 in the z8536 id register. software reads the bit as either a dce or dte value and configures the port accordingly. header j7 may be configured as follows. j7 jumper on = dte in id register j7 (factory configuration) jumper off = dce in id register 21 21 .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-19 1 figure 1-5. mvme1600-011 switches, headers, connectors, fuses, leds p1 a1 b1 c1 a32 b32 c32 11196.00 9505 (2-3) p2 a32 b32 c32 a1 b1 c1 j2 152 151 2 1 j17 j12 2 1 64 63 28 17 j5 j1 14 2 113 f1 f2 j11 2 1 64 63 19 20 1 2 j4 j3 1 2 14 15 13 12 26 25 1 2 14 15 13 12 26 25 j16 3 33 34 1 2 j6 1 3 1 j10 j14 16 15 21 j15 3 1 2 j13 1 j7 j9 j8 212121 mvme 1600-011 abt pci mezzanine card rst 10baset serial port 3 chs bfl cpu pci fus sys serial port 4 j19 1 4 .com .com .com .com .com 4 .com u datasheet
mvme1600-011 base board preparation 1-20 1 serial port 4 clock selection (j8/15/16) the mvme1600-011 is shipped from the factory with serial port 4 configured for asynchronous communications (i.e., the internal clock is used). port 4 can be configured for synchronous communications as well. it can either drive (using the internal clock) or receive (using an external clock) the receive and transmit clock signals. to select synchronous communications for the serial port 4 connection, install jumpers on headers j8, j15, and j16 in one of the configurations shown below. 3 2 1 j16 3 2 1 j16 3 2 1 j15 3 2 1 j15 (factory configuration) drive trxc4 signal receive trxc4 signal (factory configuration) drive rtxc4 signal receive rtxc4 signal j8 j8 21 21 .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-21 1 to complete the configuration of the clock lines, you must also set serial port 4 clock configuration header j15 on the mvme712m transition module (described later in this chapter). for details on the configuration of that header, refer to the mvme712m transition module section or to the users manual for the mvme712m (part number mvme712m). serial port 4 i/o path selection (j9) on the mvme1600-011, serial port 4s i/o signals are routed to backplane connector p2 and to front panel connector j3. header j9 determines the state of the dsr, ri, and tm signals on serial port 4. with a jumper installed on j9, dsr, ri, and tm come from the front panel. with the jumper removed, p2 i/o is selected. the dsr, ri, and tm signals are not supported in this case, so dsr is held true while ri and tm are held false. jumper on = front panel i/o dsr, ri, and tm from front panel to 8536 device jumper off = p2 i/o (factory configuration) dsr to 8536 device held true ri and tm to 8536 device held false j9 j9 21 21 .com .com .com .com .com 4 .com u datasheet
mvme1600-011 base board preparation 1-22 1 vmebus system controller selection (j10) the mvme1600-011 is factory-configured in system controller mode (i.e., a jumper is installed across pins 2 and 3 of header j10). this means that the mvme1600-011 assumes the role of system controller at system power-up or reset. leave the jumper installed across pins 2 and 3 if you intend to operate the mvme1600-011 as system controller in all cases. remove the jumper from j10 if the mvme1600-011 is not to operate as system controller under any circumstances. note that when the mvme1600-011 is functioning as system controller, the sys led is turned on. 3 2 1 j10 not system controller 3 2 1 j10 system controller (factory configuration) .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-23 1 serial port 3 i/o path selection (j13) on the mvme1600-011, serial port 3s i/o signals are routed to backplane connector p2 and to front panel connector j2. header j13 determines the state of the dsr, ri, and tm signals on serial port 3. with a jumper installed on j13, dsr, ri, and tm come from the front panel. with the jumper removed, p2 i/o is selected. the dsr, ri, and tm signals are not supported in this case, so dsr is held true while ri and tm are held false. general-purpose software-readable header (j14) header j14 provides eight readable jumpers. these jumpers can be read as a register at isa i/o address $80000801. bit 0 is associated with header pins 1 and 2; bit 7 is associated with pins 15 and 16. the bit values are read as a zero when the jumper is installed, and as a one when the jumper is removed. the powerpc firmware (ppcbug) reserves the four lower-order bits, srh3 to srh0. they are defined as shown in the following list: jumper on = front panel i/o dsr, ri, and tm from front panel to 8536 device jumper off = p2 i/o (factory configuration) dsr to 8536 device held true ri and tm to 8536 device held false j13 j13 21 21 .com .com .com .com .com 4 .com u datasheet
mvme1600-011 base board preparation 1-24 1 the four higher-order bits, srh4 to srh7, are user-definable. they can be allocated as necessary to specific applications. the mvme1600-011 is shipped from the factory with j14 set to all zeros (jumpers on all pins). low-order bit pins definition bit #0 (srh0) 12 reserved for future use. bit #1 (srh1) 34 with the jumper installed between pins 3 and 4 (factory configuration), the debugger uses the current user setup/operation parameters in nvram. when the jumper is removed (making the bit a 1 ), the debugger uses the default setup/operation parameters in rom instead. refer to the env command description in chapter 6 for the rom defaults. bit #2 (srh2) 56 reserved for future use. bit #3 (srh3) 78 reserved for future use. j14 2 srh7 srh6 srh5 srh1 srh4 srh3 srh2 16 15 1 srh0 user-definable user-definable user-definable setup parameter source (in=nvram; out=rom) user-definable reserved for future use reserved for future use reserved for future use ppcbug installed 87 .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-25 1 remote status and control the remote status and control connector, j4, is a keyed double-row 20-pin connector located behind the front panel of the mvme1600-011. it connects to a user-supplied external cable and carries the signals for remote reset, abort, the leds, and three general-purpose i/o signals. this allows a system designer to construct a reset/led panel that can be located remotely from the mvme1600-011. this feature is similar to the remote connector provided on the mvme167 and mvme187 single board computers; maximum cable length is 15 feet. the general-purpose i/o signals include two ttl-level i/o pins and one general-purpose interrupt pin which can also function as a trigger input. the interrupt pin is level programmable. table 1-3 lists the pin numbers, signal mnemonics, and signal descriptions for j4. .com .com .com .com .com 4 .com u datasheet
mvme1600-011 base board preparation 1-26 1 table 1-3. remote reset connector j4 interconnect signals pin number signal mnemonic signal name and description 1 +5vrmt +5 vdc power . fused through fuse f1; +5 vdc power to a user-supplied external connection. 2 lanled * lan led . signal goes low when the lan led illuminates. 3 fuseled * rpwr led . signal goes low when the fuse led illuminates. 4 scsiled * scsi led . signal goes low when the scsi led illuminates. 5 pciled * pci led . signal goes low when the pci led illuminates. 610k w pullup line. 7 runled * run led . signal goes low when the run led illuminates. 8 statled * status led . signal goes low when the status led illuminates. 9 failled * fail led . signal goes low when the fail led illuminates. 10 10k w pullup line. 11 sconled * scon led . signal goes low when the scon led illuminates. 12 abortsw * abort switch . signal goes low when the abort switch is pressed. it may be forced low externally for a remote abort. 13 resetsw * reset switch . signal goes low when the reset switch is pressed. it may be forced low externally for a remote reset. 14, 15 gnd ground . 16 10k w pullup line. 17 not used. 18 irq interrupt request . general-purpose interrupt input line. 19 spkr speaker . speaker output line. 20 gnd ground . .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-27 1 mvme712m transition module preparation the mvme712m transition module (figure 1-6) and p2 adapter board are used in conjunction with the mvme1600-011 base board. the features of the mvme712m include: o a parallel printer port (through the p2 adapter) o an ethernet interface supporting aui connections (through the p2 adapter) o four eia-232-d multiprotocol serial ports (through the p2 adapter) o an scsi interface (through the p2 adapter) for connection to both internal and external devices o socket-mounted scsi terminating resistors for end-of-cable or middle-of-cable configurations o provision for modem connection o green led for scsi terminator power; yellow led for ethernet transceiver power the features of the p2 adapter board include: o a 50-pin connector for scsi cabling to the mvme712m and/or to other scsi devices o socket-mounted scsi terminating resistors for end-of-cable or middle-of-cable configurations o fused scsi teminator power developed from the +5vdc present at connector p2 o a 64-pin din connector to interface the eia-232-d, parallel, scsi, and ethernet signals to the mvme712m .com .com .com .com .com 4 .com u datasheet
mvme712m transition module preparation 1-28 1 figure 1-6. mvme712m connector and header locations j7 1 2 j9 13 25 13 25 1 14 1 14 j8 j10 13 25 13 25 1 14 1 14 1 8 9 15 j6 18 1 19 8 1 r51 c1 c2 c3 j2 j3 1 50 49 a1 c1 c32 a32 2 1 14 13 j1 2 1 14 13 j13 2 1 14 13 j16 2 1 14 13 j18 8 1 r50 8 1 r49 2 1 14 13 j11 2 1 14 13 j14 2 1 14 13 j17 2 1 14 13 j19 2 1 20 19 16 j21 j20 212 j15 11 1 2 49 50 ds2 ds1 j5 j4 cb228 9212 ethernet printer mvme712m serial port 1 / console serial port 3 serial port 2 / tty01 serial port 4 scsi interface primary side 36 .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-29 1 serial ports 1-4 dce/dte configuration serial ports 1 through 4 are configurable as modems (dce) for connection to terminals, or as terminals (dte) for connection to modems. the mvme712m is shipped with the serial ports configured for dte operation. serial port dce/dte configuration is accomplished by positioning jumpers on one of two headers per port.the following table lists the serial ports with their corresponding jumper headers. serial port 4 clock configuration port 4 can be configured via j15 (figure 1-7) to use the trxc4 and rtxc4 signal lines. part of the configuration must be done with headers j8, j15, and j16 on the mvme1600-011 (figure 1-8). figure 1-7. j15 clock line configuration serial port board connector panel connector jumper header port 1 j7 serial port 1/ console j1/j11 port 2 j8 serial port 2/ tty j16/j17 port 3 j9 serial port 3 j13/j14 port 4 j10 serial port 4 j18/j19 trxc4 to port 4 pin 15 trxc4 to port 4 pin 17 trxc4 to port 4 pin 24 rtxc4 to port 4 pin 24 rtxc4 to port 4 pin 17 rtxc4 to port 4 pin 15 j15 3 1 9 57 11 .com .com .com .com .com 4 .com u datasheet
mvme712m transition module preparation 1-30 1 figure 1-8. mvme1600-011 serial port 4 clock configuration z85230 scc p2 adapter board 64 pin cable mvme712m transition board txd dtr rts rtxc rrxc ttxc gnd rxd dcd cts db25 2 20 4 15 17 24 7 3 8 5 11202.00 9502 trxc4 rtxc4 j15 1 txdb rtsb* rxdb ctsb* rxdb dcdb* ctsb* trxcb txd rts rxd cts dcd txci txco rxci dcdb* rtxcb 2 4 3 5 8 15 24 17 front hd26 pa nel z8536 cio (pb5) dtr4* (pb3) llb4* (pb4) rlb4* (pb1) dsr4* (pb2) ri4* (pb0 tm4* dtr llb rlb dsr ri tm gnd j15 j16 20 18 21 6 22 25 7 j8 .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-31 1 preparation of the p2 adapter for the mvme712m consists of removing or installing the scsi terminating resistors. figure 1-9 illustrates the location of the resistors, fuse, and connectors. for further information on the preparation of the transition module and the p2 adapter, refer to the users manual for the mvme712m (part number mvme712m) as necessary. figure 1-9. p2 adapter component placement c1 b1 a1 c32 b32 a32 2 1 50 49 r2 r3 r1 c1 c2 c3 f1 p2 cr1 1 1 2 a1 b1 c1 a32 b32 c32 j2 j3 cb211 9212 .com .com .com .com .com 4 .com u datasheet
hardware installation 1-32 1 hardware installation the following sections discuss the placement of the various mezzanine cards on the the mvme1600-001 and the mvme1600-011 base boards, the installation of the complete MVME1603/1604 vmemodule assembly and corresponding transition module into a vme chassis, and the system considerations relevant to the installation. before installing the MVME1603/1604, ensure that the serial ports and all header jumpers are configured as desired. in most cases, the mezzanine cardsthe processor/memory module, the led mezzanine, the dram module, and (if applicable) the optional pci mezzanineare already in place on the MVME1603/1604. the user- configurable jumpers are accessible with the mezzanines installed. should it be necessary to install mezzanines on the base board, refer to the following sections for a brief description of the installation procedure. if necessary, you can find additional information in the users manuals for the individual mezzanine cards. esd precautions motorola strongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system. electronic components, such as disk drives, computer boards, and memory modules, can be extremely sensitive to esd. after removing the component from the system or its protective wrapper, place the component flat on a grounded, static-free surface (and in the case of a board, component side up). do not slide the component over any surface. if an esd station is not available, you can avoid damage resulting from esd by wearing an antistatic wrist strap (available at electronics stores) that is attached to an unpainted metal part of the system chassis. use esd wrist strap .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-33 1 pm603/604 processor/memory mezzanine to install a pm603 or pm604 processor/memory mezzanine on an MVME1603/1604 main module, refer to figure 1-10 and proceed as follows: 1. attach an esd strap to your wrist. attach the other end of the esd strap to the chassis as a ground. the esd strap must be secured to your wrist and to ground throughout the procedure. 2. perform an operating system shutdown. turn the ac or dc power off and remove the ac cord or dc power lines from the system. remove chassis or system cover(s) as necessary for access to the vmemodules. ! caution inserting or removing modules with power applied may result in damage to module components. ! warning dangerous voltages, capable of causing death, are present in this equipment. use extreme caution when handling, testing, and adjusting. 3. carefully remove the MVME1603/1604 from its vmebus card slot and lay it flat, with connectors p1 and p2 (the rear panel) facing you. ! caution avoid touching areas of integrated circuitry; static discharge can damage these circuits ! caution the 192mb module is a factory-installed option. it is recommended that you do not attempt to remove it, as the components could easily be damaged. 4. place the pm603 or pm604 mezzanine module on top of the MVME1603/1604, with the cutout corner at the upper right. connector j5 at the bottom edge of the pm603 or pm604 should connect smoothly with its corresponding connector on the MVME1603/1604. .com .com .com .com .com 4 .com u datasheet
pm603/604 processor/memory mezzanine 1-34 1 figure 1-10. pm603/pm604 placement on MVME1603/1604 j3 j5 j2 j4 pm603/pm604 11197.00 9411 (1-2) .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-35 1 5. align the standoffs on the MVME1603/1604 board with the holes at the edges of the pm603 or pm604 mezzanine, insert the phillips screws through the holes in the mezzanine and the spacers, and tighten the screws. 6. reinstall the MVME1603/1604 assembly in its proper card slot. be sure the module is seated properly in the backplane connectors. do not damage or bend connector pins. 7. replace the chassis or system cover(s), reconnect the system to the ac or dc power source, and turn the equipment power on. ram104 memory mezzanine installation the ram104 dram mezzanine mounts on top of the pm603 or pm604 processor/memory mezzanine. to install a ram104 mezzanine, refer to figure 1-11 and proceed as follows: 1. attach an esd strap to your wrist. attach the other end of the esd strap to the chassis as a ground. the esd strap must be secured to your wrist and to ground throughout the procedure. 2. perform an operating system shutdown. turn the ac or dc power off and remove the ac cord or dc power lines from the system. remove chassis or system cover(s) as necessary for access to the vmemodules. ! caution inserting or removing modules with power applied may result in damage to module components. ! warning dangerous voltages, capable of causing death, are present in this equipment. use extreme caution when handling, testing, and adjusting. .com .com .com .com .com 4 .com u datasheet
ram104 memory mezzanine installation 1-36 1 figure 1-11. ram104 placement on pm603/pm604 j2 j5 j2 j1 pm603/pm604 ram104 .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-37 1 3. carefully remove the MVME1603/1604 from its vmebus card slot and lay it flat on an esd mat, component side up, with connectors p1 and p2 facing you and the pm603/pm604 corner cutout at the upper right. the esd mat should be on a firm, flat surface. ! caution avoid touching areas of integrated circuitry; static discharge can damage these circuits 4. remove the four short phillips screws from the holes at the top corners and the middle of the pm603/pm604. 5. pick up the ram104 mezzanine module, and note the positions of the male guide pins on the ram104 connectors j1 and j2 at its left and right edges. also note the positions of the female guide pins on the pm603/pm604 connectors. align the ram104 connectors j2 and j1 with the corresponding connectors j3 and j4 on the pm603/pm604, without actually setting the ram104 on the pm603/pm604. 6. place the ram104 mezzanine module on top of the pm603 or pm604 mezzanine. do not press the boards together yet. 7. visually verify that the male guide pins on the ram104 connectors are aligned with the female guide pins on the pm603/pm604 connectors. you can only see the guide pins from the sides. do not press the boards together yet. ! caution failure to properly align the connectors on the ram104 and the pm603/pm604 may result in damage to the modular components. 8. place your thumbs on the top side of the ram104 mezzanine module, in the middle of and behind each connector (j1 and (j2). press firmly down with both thumbs until the ram104 and the pm603/pm604 click together. 9. visually verify that the connectors are fully seated. connectors j2 and j1 at the left and right edges of the ram104 should be connected with the corresponding connectors j3 and j4 on the pm603/pm604. 10. insert two long phillips screws through the holes at the top corners of the ram104 module and into the standoffs on the mvme160x. .com .com .com .com .com 4 .com u datasheet
MVME1603/1604 vmemodule installation 1-38 1 install two similar screws in the bottom (tabbed) corners of the ram104. tighten the screws. 11. reinstall the MVME1603/1604 assembly in its proper card slot. be sure the module is seated properly in the backplane connectors. do not damage or bend connector pins. 12. replace the chassis or system cover(s), reconnect the system to the ac or dc power source, and turn the equipment power on. MVME1603/1604 vmemodule installation with mezzanine boards installed and headers properly configured, proceed as follows to install the MVME1603/1604 in the vme chassis: 1. attach an esd strap to your wrist. attach the other end of the esd strap to the chassis as a ground. the esd strap must be secured to your wrist and to ground throughout the procedure. 2. perform an operating system shutdown. turn the ac or dc power off and remove the ac cord or dc power lines from the system. remove chassis or system cover(s) as necessary for access to the vmemodules. ! caution inserting or removing modules with power applied may result in damage to module components. ! warning dangerous voltages, capable of causing death, are present in this equipment. use extreme caution when handling, testing, and adjusting. 3. remove the filler panel from the card slot where you are going to install the MVME1603/1604. C if you intend to use the MVME1603/1604 as system controller, it must occupy the leftmost card slot (slot 1). the system controller must be in slot 1 to correctly initiate the bus-grant daisy-chain and to ensure proper operation of the iack daisy- chain driver. .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-39 1 C if you do not intend to use the MVME1603/1604 as system controller, it can occupy any unused double-height card slot. 4. slide the MVME1603/1604 into the selected card slot. be sure the module is seated properly in the p1 and p2 connectors on the backplane. do not damage or bend connector pins. ! caution avoid touching areas of integrated circuitry; static discharge can damage these circuits 5. secure the MVME1603/1604 in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize rf emissions. 6. on the chassis backplane, remove the interrupt acknowledge (iack) and bus grant (bg) jumpers from the header for the card slot occupied by the MVME1603/1604. note some vme backplanes (e.g., those used in motorola modular chassis systems) have an autojumpering feature for automatic propagation of the iack and bg signals. step 6 does not apply to such backplane designs. 7. replace the chassis or system cover(s), cable peripherals to the panel connectors as appropriate, reconnect the system to the ac or dc power source, and turn the equipment power on. mvme760 transition module installation the mvme760 transition module is used in conjunction with the mvme1600-001 base board. with the MVME1603/1604 installed, refer to figure 1-12 and proceed as follows to install an mvme760 transition module: .com .com .com .com .com 4 .com u datasheet
mvme760 transition module installation 1-40 1 1. attach an esd strap to your wrist. attach the other end of the esd strap to the chassis as a ground. the esd strap must be secured to your wrist and to ground throughout the procedure. 2. perform an operating system shutdown. turn the ac or dc power off and remove the ac cord or dc power lines from the system. remove chassis or system cover(s) as necessary for access to the vmemodules. ! caution inserting or removing modules with power applied may result in damage to module components. ! warning dangerous voltages, capable of causing death, are present in this equipment. use extreme caution when handling, testing, and adjusting. 3. remove the filler panel(s) from the appropriate card slot(s) at the front or rear of the chassis. (you may need to shift other modules in the chassis to allow space for the cables connected to the mvme760 transition module.) 4. attach the flat ribbon cable supplied with the mvme760 to the p2 backplane connector at the slot occupied by the mvme1600-001 base board. route the cable to p2 on the transition module. be sure to orient cable pin 1 with connector pin 1. ! caution avoid touching areas of integrated circuitry; static discharge can damage these circuits 5. secure the mvme760 in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize rf emissions. 6. replace the chassis or system cover(s), making sure no cables are pinched. cable the peripherals to the panel connectors, reconnect the system to the ac or dc power source, and turn the equipment power on. .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-41 1 note not all peripheral cables are provided with the mvme760; you may need to fabricate or purchase certain cables. (motorola recommends shielded cable for all peripheral connections to minimize radiation.) figure 1-12. mvme760/mvme1600-001 cable connections p2 p2 p1 enclosure boundary mvme760 mvme1600-001 j1 j3 j5 j10 j11 j12 1548 9412 p2 .com .com .com .com .com 4 .com u datasheet
mvme712m transition module installation 1-42 1 mvme712m transition module installation the mvme712m transition module is used in conjunction with the mvme1600-011 base board. with the MVME1603/1604 installed, refer to figure 1-13 and proceed as follows to install an mvme712m transition module: 1. attach an esd strap to your wrist. attach the other end of the esd strap to the chassis as a ground. the esd strap must be secured to your wrist and to ground throughout the procedure. 2. perform an operating system shutdown. turn the ac or dc power off and remove the ac cord or dc power lines from the system. remove chassis or system cover(s) as necessary for access to the vmemodules. ! caution inserting or removing modules with power applied may result in damage to module components. ! warning dangerous voltages, capable of causing death, are present in this equipment. use extreme caution when handling, testing, and adjusting. 3. remove the filler panel(s) from the appropriate card slot(s) at the front or rear of the chassis. (you may need to shift other modules in the chassis to allow space for the mvme712m, which has a double- wide front panel.) 4. attach the p2 adapter board and cable(s) to the p2 backplane connector at the slot occupied by the mvme1600-011 base board. 5. route the 64-conductor cable to p2 on the transition module. be sure to orient cable pin 1 with connector pin 1. ! caution avoid touching areas of integrated circuitry; static discharge can damage these circuits .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-43 1 6. secure the mvme712m in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize rf emissions. 7. route the 50-conductor cable to the internal or external scsi devices as appropriate to your system configuration. be sure to orient cable pin 1 with connector pin 1. note the scsi cabling can be configured in a number of ways to accommodate various device and system configurations. figure 1-13 shows a possible configuration for use with internal scsi devices. for more detailed information on installing the p2 adapter board and the mvme712m transition module, refer to the mvme712m transition module and p2 adapter board users manual . 8. replace the chassis or system cover(s), making sure no cables are pinched. cable the peripherals to the panel connectors, reconnect the system to the ac or dc power source, and turn the equipment power on. note not all peripheral cables are provided with the mvme712m; you may need to fabricate or purchase certain cables. (motorola recommends shielded cable for all peripheral connections to minimize radiation.) .com .com .com .com .com 4 .com u datasheet
mvme712m transition module installation 1-44 1 figure 1-13. mvme712m/mvme1600-011 cable connections j6 j2 scsi device mvme1600-011 p1 p2 j3 enclosure boundary terminators installed terminators removed 50-conductor cable terminators installed mvme712m cb2349301 scsi device p2 adapter p2 t j3 j2 j9 j7 j8 j10 j4 j5 64-conductor cable .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-45 1 system considerations the MVME1603/1604 draws power from vmebus backplane connectors p1 and p2. p2 is also used for the upper 16 bits of data in 32-bit transfers, and for the upper 8 address lines in extended addressing mode. the MVME1603/1604 may not function properly without its main board connected to vmebus backplane connectors p1 and p2. whether the MVME1603/1604 operates as a vmebus master or as a vmebus slave, it is configured for 32 bits of address and 32 bits of data (a32/d32). however, it handles a16 or a24 devices in the address ranges indicated in chapter 2. d8 and/or d16 devices in the system must be handled by the powerpc? processor software. refer to the memory maps in chapter 2. the MVME1603/1604 contains shared onboard dram (and, optionally, secondary cache memory) whose base address is software-selectable. both the onboard processor and offboard vmebus devices see this local dram at base physical address $00000000, as programmed by the ppcbug firmware. this may be changed via software to any other base address. refer to the MVME1603/mvme1604 single board computer programmer's reference guide for more information. if the MVME1603/1604 tries to access offboard resources in a nonexistent location and is not system controller, and if the system does not have a global bus timeout, the MVME1603/1604 waits forever for the vmebus cycle to complete. this will cause the system to lock up. there is only one situation in which the system might lack this global bus timeout: when the MVME1603/1604 is not the system controller and there is no global bus timeout elsewhere in the system. multiple MVME1603/1604s may be installed in a single vme chassis. in general, hardware multiprocessor features are supported. note if you are installing multiple MVME1603/1604s in an mvme945 chassis, do not install an MVME1603/1604 in slot 12. the extra thickness of the module may cause clearance difficulties in that slot position. .com .com .com .com .com 4 .com u datasheet
system considerations 1-46 1 other mpus on the vmebus can interrupt, disable, communicate with, and determine the operational status of the processor(s). one register of the gcsr (global control/status register) set includes four bits that function as location monitors to allow one MVME1603/1604 processor to broadcast a signal to any other MVME1603/1604 processors. all eight registers are accessible from any local processor as well as from the vmebus. the mvme1600-001 and mvme1600-011 base boards draw +5vdc, +12vdc, and C12vdc power from the vmebus backplane through connectors p1 and p2. the 3.3vdc power (used by the isa super i/o device on the base board, and by the pm603 or pm604 processor/memory mezzanine) is derived on-board from the +5vdc. mvme1600-001 base board the mvme1600-001 base board furnishes +12vdc, C12vdc, and +5vdc power to the mvme760 transition module through polyswitches (resettable fuses) f4, f2, and f3. the mvme760 uses these voltage sources to power the serial port drivers and any lan transceivers connected to the transition module. the fus led (ds5) on the mvme1600-001 front panel illuminates when all three voltages are available. the fused +5vdc power is also supplied to the base boards keyboard and mouse connectors and to the 14-pin combined led-mezzanine/remote- reset connector, j1. in addition, the mvme1600-001 base board provides +5vdc to the scsi bus termpwr signal through fuse f1, located near the front panel scsi connector. the fus led (ds5) on the front panel monitors the scsi bus termpwr signal along with the other operating voltages; when the mvme1600-001 is connected to an scsi bus, either directly or via the mvme760 module, scsi terminator power helps illuminate the fus led. .com .com .com .com .com 4 .com u datasheet
hardware preparation and installation 1-47 1 note because any device on the scsi bus can provide termpwr , and because the fus led monitors the status of several voltages, the led does not directly indicate the condition of any single fuse. if the led flickers or goes out, check all the fuses (polyswitches). the mvme1600-001 base board supplies a speaker_out signal to the 14-pin combined led-mezzanine/remote-reset connector, j1. when j1 is used as a remote reset connector with the led mezzanine removed, the speaker_out signal can be cabled to an external speaker. for the pin assignments of j1, refer to table 1-2. mvme1600-011 base board the mvme1600-011 base board provides +5vdc power to the remote led/switch connector (j4) through a 1a fuse (f1) located between p1 and p2. (j4 provides a separate connection point for a remote control and indicator panel, making it unnecessary to share the led mezzanine connector for that purpose.) if none of the leds light and the abort and reset switches do not operate, check fuse f1. the mvme1600-011 base board provides +12vdc power to the ethernet transceiver interface through a 1a fuse (f2) located between p1 and p2. the fus led lights to indicate that +12vdc is available. with the mvme712m transition module connected, the yellow ds1 led on the mvme712m also signals the availability of lan power, indicating in turn that the fuse is good. if the ethernet transceiver fails to operate, check fuse f2. the mvme1600-011 base board supplies scsi terminator power through a 1a fuse (f1) located on the p2 adapter board. if the fuse is blown, the scsi device(s) may function erratically or not at all. with the p2 adapter board cabled to an mvme712m and with an scsi bus connected to the mvme712m, the green ds2 led on the mvme712m illuminates when scsi terminator power is available. if the ds2 led flickers during scsi bus operation, check fuse f1 on the p2 adapter board. .com .com .com .com .com 4 .com u datasheet
system considerations 1-48 1 like the mvme1600-001 base board, the mvme1600-011 supplies a speaker_out signal to the 14-pin led mezzanine connector, j1. unlike the mvme1600-001 base board, the mvme1600-011 also applies the speaker_out signal to the dedicated remote status and control connector, j4. the led mezzanine need not be removed to cable the speaker_out signal to an external speaker. for the pin assignments of j4, refer to table 1-3. .com .com .com .com .com 4 .com u datasheet
2 2-1 2 operating instructions introduction this chapter provides information for use of the MVME1603/1604 family of single board computers in a system configuration. here you will find the power-up procedure and descriptions of switches and leds; memory maps; and software initialization. applying power after you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is complete, you can power up the system. when power is applied, the ppcbug firmware executes various self-tests and then displays the debugger prompt ppc1-bug (if the firmware is in bug mode). if the firmware was previously placed in system mode, it displays the prompt ppc1-diag , performs self-tests, and tries to autoboot. you can press esc to skip the self-tests, or press abort or break to interrupt them. for further information on the ppcbug firmware, refer to chapter 5, ppcbug , appendix d, troubleshooting cpu boards , or to the ppcbug firmware package users manual . the MVME1603/1604 front panel has abort and reset switches and six led (light-emitting diode) status indicators ( chs , bfl , cpu , pci , fus , sys ). the switches and leds are mounted on an led mezzanine board that plugs into the base board. abort switch (s1) when activated by software, the abort switch can generate an interrupt signal from the base board to the processor at a user-programmable level. the interrupt is normally used to abort program execution and return control to the ppcbug debugger firmware located in the .com .com .com .com .com 4 .com u datasheet
applying power 2-2 2 MVME1603/1604 eprom and flash memory. the interrupt signal reaches the processor module via isa bus interrupt line irq8 * . the signal is also available at pin pb7 of the z8536 cio device, which handles various status signals, serial i/o lines, and counters. the interrupter connected to the abort switch is an edge-sensitive circuit, filtered to remove switch bounce. reset switch (s2) the reset switch resets all onboard devices; it also drives a sysreset * signal if the MVME1603/1604 is the system controller. the reset switch may be disabled by software. the vmechip2 includes both a global and a local reset driver. when the vmechip2 operates as the vmebus system controller, the reset driver provides a global system reset by asserting the vmebus signal sysreset * . a sysreset * signal may be generated by the reset switch, a power-up reset, a watchdog timeout, or by a control bit in the lcsr in the vmechip2. sysreset * remains asserted for at least 200 ms, as required by the vmebus specification. similarly, the vmechip2 supplies an input signal and a control bit to initiate a local reset operation. by setting a control bit, software can maintain a board in a reset state, disabling a faulty board from participating in normal system operation. the local reset driver is enabled even when the vmechip2 is not system controller. local resets may be generated by the reset switch, a power-up reset, a watchdog timeout, a vmebus sysreset * , or a control bit in the gcsr. note for an MVME1603/1604 without the vmebus option (i.e., with no vmechip2), the lcsr control bit is not available to reset the module. in this case, the watchdog timer is allowed to time out to reset the MVME1603/1604. .com .com .com .com .com 4 .com u datasheet
operating instructions 2-3 2 front panel indicators (ds1 - ds6) there are six leds on the MVME1603/1604 front panel: chs , bfl , cpu , pci , fus , and sys . o chs (ds1, yellow). checkstop; driven by the mpc603/604 status lines on the MVME1603/1604. lights when a halt condition from the processor is detected. o bfl (ds2, yellow). board failure; lights when the brdfail * signal line is active. o cpu (ds3, green). cpu activity; lights when the dbb * (data bus busy) signal line on the processor bus is active. o pci (ds4, green). pci activity; lights when the irdy * (initiator ready) signal line on the pci bus is active. this indicates that the pci mezzanine (if installed) is active. o fus (ds5, green). fuse ok; lights when +5vdc, +12vdc, and C 12vdc power is available from the base board to the transition module and remote devices. note the circuitry monitored by the fus led differs between the mvme1600-001 and mvme1600-011 versions of the base board. the differences are detailed under the respective base board descriptions in chapter 1. because the fus led monitors the status of several voltages on the mvme1600-001, it does not directly indicate the condition of any single fuse. if the led flickers or goes out, check all the fuses (polyswitches). o sys (ds6, green). system controller; lights when the vmechip2 in the MVME1603/1604 is the vmebus system controller. .com .com .com .com .com 4 .com u datasheet
memory maps 2-4 2 memory maps there are three points of view for memory maps: o the mapping of all resources as viewed by the processor (mpu bus memory map) o the mapping of onboard resources as viewed by pci local bus masters (pci bus memory map) o the mapping of onboard resources as viewed by vmebus masters (vmebus memory map) the following sections describe the MVME1603/1604 memory organization from the above three points of view. additional, more detailed memory maps can be found in the programmers reference guide (part number v1600-1a/pg). mpu bus memory map the mpu bus memory map is split into different address spaces by the transfer type (tt) signals. the local resources respond to the normal access and interrupt acknowledge codes. normal address range the memory map of devices that respond to the normal address range is shown in the following tables. the normal address range is defined by the tt signals on the mpu bus. for the MVME1603/1604, transfer types 0, 1, and 2 define the normal address range. table 2-1 defines the entire map ($00000000 to $ffffffff). many areas of the map are user- programmable, and suggested uses are shown in the table. the cache inhibit function is programmable in the powerpc 603/604 microprocessor mmu. the onboard i/o space must be marked cache inhibit and serialized in its page table. table 2-2 further defines the map for the local i/o devices (accessible through the directly mapped pci configuration space). .com .com .com .com .com 4 .com u datasheet
operating instructions 2-5 2 notes 1. pci configuration accesses to cf8 (configuration address) and cfc (configuration data) are supported by the mpc105 pci bridge/memory controller as specified in the pci specification revision 2.0. 2. both contiguous and discontiguous mappings are supported by the MVME1603/1604. refer to the isa/pci i/o space mapping table for more details. 3. this space is used for direct mapped pci configuration space accesses. refer to the pci configuration space mapping section for more details. 4. eprom/flash decoding repeats every 1mb for this entire 16mb range. 5. the usage of this 14mb address range for eprom/flash is not recommended, since future powerpc products will redefine this area. 6. the m48t18 rtc and nvram device is mapped in this area. refer to the isa/pci i/o space mapping table for more details. 7. a read of any byte within this 16-byte range (bffffff0 through bfffffff) causes a pci iack cycle. the data read is the iack vector. table 2-1. processor view of the memory map processor address size pci address generated definition notes start end start end 00000000 7fffffff 2gb dram - not forwarded to pci 80000000 807fffff 8mb 00000000 007fffff isa/pci i/o space 1, 2, 6 80800000 80ffffff 8mb 00800000 00ffffff pci configuration space (direct map) 3 81000000 bf7fffff 1gb-24mb 01000000 3f7fffff pci i/o space bf800000 bfffffef 8mb -16b reserved bffffff0 bfffffff 16b 3ffffff0 3fffffff pci iack/ special cycles 7 c0000000 c0ffffff 16mb 00000000 00ffffff pci/isa memory space c1000000 feffffff 1gb-32mb 01000000 3effffff pci memory space ff000000 ff07ffff 512kb eprom/flash bank 0 4 ff080000 ff0fffff 512kb eprom/flash bank 1 4 ff100000 ffefffff 14mb reserved 4, 5 fff00000 fff7ffff 512kb eprom/flash bank 0 repeat 4 fff80000 ffffffff 512kb eprom/flash bank 1 repeat 4 .com .com .com .com .com 4 .com u datasheet
memory maps 2-6 2 table 2-2 focuses on the map for the local i/o devices (accessible through the directly mapped pci configuration space). note accesses to reserved space may select multiple devices and produce unpredictable results. table 2-2. pci configuration space memory map idsel processor address pci address generated definition start end start end 80800000 808007ff 00800000 008007ff reserved a11 80800800 808008ff 00800800 008008ff ibc configuration registers (pci/isa bridge) 80800900 80800fff 00800900 00800fff reserved a12 80801000 808010ff 00801000 008010ff 53c810/825 configuration registers (scsi) 80801100 80801fff 00801100 00801fff reserved a13 80802000 808020ff 00802000 008020ff vme2pci configuration registers (vmebus) 80802100 80803fff 00802100 00803fff reserved a14 80804000 808040ff 00804000 008040ff decchip 21040 configuration registers (ethernet) 80804100 80807fff 00804100 00807fff reserved a15 80808000 808080ff 00808000 008080ff gd5446 configuration registers (graphics) 80808100 8080ffff 00808100 0080ffff reserved a16 80810000 808100ff 00810000 008100ff pmc slot configuration registers (pci mezzanine) 80810100 80ffffff 00810100 00ffffff reserved .com .com .com .com .com 4 .com u datasheet
operating instructions 2-7 2 table 2-3 focuses on the mapping of the isa/pci i/o space from the processor view of the memory map. table 2-3. isa/pci i/o space memory map isa i/o address processor address function notes contiguous discontiguous 0000-000f 8000 0000 - 8000 000f 8000 0000 - 8000 000f ibc: dma1 registers & control 2 0020-0021 8000 0020 - 8000 0021 8000 1000 - 8000 1001 ibc: interrupt 1 control & mask 2 0040-0043 8000 0040 - 8000 0043 8000 2000 - 8000 2003 ibc: timer counter 1 registers 2 0060 8000 0060 8000 3000 ibc: reset ubus irq12 2 0061 8000 0061 8000 3001 ibc: nmi status and control 2 0064 8000 0064 8000 3004 isasio: keyboard controller port 3 0074 8000 0074 8000 3014 nvram/rtc address strobe 0 0075 8000 0075 8000 3015 nvram/rtc address strobe 1 0077 8000 0077 8000 3017 nvram/rtc data port 0080-0090 8000 0080 - 8000 0090 8000 4000 - 8000 4010 ibc: dma page registers 2 0092 8000 0092 8000 4012 ibc: port 92 register 2 0094-009f 8000 0094 - 8000 009f 8000 4014 - 8000 401f ibc: dma page registers 2 00a0-00a1 8000 00a0 - 8000 00a1 8000 5000 - 8000 5001 ibc: interrupt 2 control & mask 2 00c0-00cf 8000 00c0 - 8000 00cf 8000 6000 - 8000 600f ibc: dma2 address registers 2 00d0-00df 8000 00d0 - 8000 00df 8000 7000 - 8000 700f ibc: dma2 control registers 2 02f8-02ff 8000 02f8 - 8000 02ff 8001 7018 - 8001 701f isasio: serial port 2 (com2) 3 0398 8000 0398 8001 c018 isasio index register 2 0399 8000 0399 8001 c019 isasio data register 2 03bc-03bf 8000 03bc - 8000 03bf 8001 d01c - 8001 d01f isasio: parallel port (lpt1) 3 03f0-03f7 8000 03f0 - 8000 03f7 8001 f010 - 8001 f017 isasio: floppy drive controller (fdc) 3 03f8-03ff 8000 03f8 - 8000 03ff 8001 f018 - 8001 f01f isasio: serial port 1 (com1) 3 040a 8000 040a 8002 000a ibc: scatter/gather interrupt status register 2 .com .com .com .com .com 4 .com u datasheet
memory maps 2-8 2 040b 8000 040b 8002 000b ibc: dma1 extended mode register 2 0410-041f 8000 0410 - 8000 041f 8002 0010 - 8002 001f ibc: dma scatter/gather command and status registers 2 0420-042f 8000 0420 - 8000 042f 8002 1000 - 8002 100f ibc: dma ch0-ch3 scatter/gather descriptor table pointers 2 0430-043f 8000 0430 - 8000 043f 8002 1010 - 8002 101f ibc: dma ch4-ch7 scatter/gather descriptor table pointers 2 0481-048b 8000 0481 - 8000 048b 8002 4001 - 8002 400b ibc: dma high page registers 2 04d0 8000 04d0 8002 6010 ibc: int1 edge level control 2 04d1 8000 04d1 8002 6011 ibc: int2 edge level control 2 04d6 8000 04d6 8002 6016 ibc: dma2 extended mode register 2 0c04 8000 0c04 8006 0004 ibc: power control output port 2, 4 0c01 8000 0c01 8006 0001 ibc: test mode control port/shadow reg- ister of port 70 2, 4 0800 8000 0800 8004 0000 cpu configuration register 4, 6 0801 8000 0801 8004 0001 software readable header 4 0802 8000 0802 8004 0002 board configuration register 4 0803 8000 0803 8004 0003 reserved 4 0804 8000 0804 8004 0004 dram size register 4, 6 0805 8000 0805 8004 0005 reserved 4 0806 8000 0807 8004 0006 reserved 4 0807 8000 0807 8004 0007 reserved 4 0820 8000 0820 8004 1000 reserved for cooling monitor 4 0830 8000 0830 8004 1010 reserved for audio 4 0840 8000 0840 8004 2000 z85230: port b (serial port 4) control 4 0841 8000 0841 8004 2001 z85230: port b (serial port 4) data 4 0842 8000 0842 8004 2002 z85230: port a (serial port 3) control 4 0843 8000 0843 8004 2003 z85230: port a (serial port 3) data 4 0844 8000 0844 8004 2004 z8536 cio: port cs data register 4 0845 8000 0845 8004 2005 z8536 cio: port bs data register 4 0846 8000 0846 8004 2006 z8536 cio: port as data register 4 0847 8000 0847 8004 2007 z8536 cio: control register 4 084f 8000 084f 8004 200f z85230/z8536 pseudo iack 4, 5 table 2-3. isa/pci i/o space memory map (continued) isa i/o address processor address function notes contiguous discontiguous .com .com .com .com .com 4 .com u datasheet
operating instructions 2-9 2 notes 1. all isa i/o locations not specified in this table are reserved. 2. these locations are internally decoded by the ibc (pci/isa bridge). 3. these locations are internally decoded by the isasio (isa super i/o controller). 4. these locations are either not specified by the powerpc reference platform (prp) specification or are not prp-compliant. they may overlap some other functions specified by the prp specification. 5. an iack vector is returned from either the z8536 or the z85230 when this location is read. 6. these registers physically reside on the pm603/604 module. 7. the board comes up in contiguous mode. contiguous and discontiguous modes are programmed by the mpc105 pci bridge/memory controller. ! caution the ppcbug debugger and several operating systems execute in contiguous mode. if this is changed to discontiguous mode, ppcbug will cease to function correctly. pci local bus memory map table 2-4 shows the mapping of onboard resources from the point of view of the pci local bus. table 2-4. pci view of the memory map pci address size processor bus address definition notes start end start end 00000000 00ffffff 16mb not forwarded to mpu bus pci/isa memory space 1, 2 01000000 7fffffff 2gb- 16mb not forwarded to mpu bus pci memory space 2 80000000 ffffffff 2gb 00000000 7fffffff onboard dram (via mpc105) 00000000 ffffffff 4gb not forwarded to mpu bus pci/isa i/o space .com .com .com .com .com 4 .com u datasheet
memory maps 2-10 2 notes 1. the ibc (pci/isa bridge) performs subtractive decoding in this range and forwards the pci memory cycle to the isa if devsel * is not detected. 2. the vme2pci asic can be programmed to claim some of this address range to forward the pci memory cycle to the vmechip2. vmebus memory map the vmebus is programmable. the mapping of local resources as viewed by vmebus masters varies among applications. the vmechip2 asic includes a user-programmable map decoder for the vmebus-to-local-bus interface. the map decoder enables you to program the starting and ending address and the modifiers to which the MVME1603/1604 responds. the vmechip2 also includes a user-programmable map decoder for the gcsrs (global control/status registers, accessible from both the vmebus and the local bus). the gcsr map decoder allows you to program the starting address of the gcsrs in the vmebus short i/o space. the vme2pci asic supplies the interface between the pci local bus and the vmechip2 asic. table 2-5 shows the mapping of onboard resources from the point of view of the vme2pci. .com .com .com .com .com 4 .com u datasheet
operating instructions 2-11 2 table 2-6 shows the mapping of onboard resources from the point of view of the vmechip2. table 2-5. vme2pci view of the memory map processor address pci configuration address register name read/write reset value (hexadecimal) 80802000 00802000 pci vendor id r 1057h 80802002 00802002 pci device id r 4800h 80802004 00802004 pci command r/w 0000h 80802006 00802006 pci status r/w 0000h 80802008 00802008 pci revision id r 01 80802009 00802009 pci class code r 068000h 8080200c 0080200c pci cache line size r/w 00h 8080200d 0080200d pci latency timer r/w 00h 8080200e 0080200e pci header type r 00h 80802010 00802010 pci i/o base address r/w 00000001h 80802014 00802014 pci memory base address r/w 00000000h 8080203c 0080203c pci interrupt line r/w 00h 8080203d 0080200d pci interrupt pin r 01h 8080203e 0080200e pci minimum grant r 00 8080203f 0080200f pci maximum latency r 00 80802040 00802040 slave starting address 1 r/w 0000h 80802042 00802042 slave ending address 1 r/w 0000h 80802044 00802044 slave address offset 1 r/w 0000h 80802046 00802046 slave address enable 1 r/w 00h 80802048 00802048 slave starting address 2 r/w 0000h 8080204a 0080204a slave ending address 2 r/w 0000h 8080204c 0080204c slave address offset 2 r/w 0000h 8080204d 0080204d slave address enable 2 r/w 00h 80802050 00802050 interrupt status and control r/w 0000h .com .com .com .com .com 4 .com u datasheet
memory maps 2-12 2 table 2-6. vmechip2 memory map (sheet 1 of 3) dma tb snp mode rom zero sram speed adder 2 slave ending address 1 slave ending address 2 slave address translation address 1 slave address translation address 2 blk d64 snp 2 wp 2 sup 2 usr 2 a32 2 a24 2 blk 2 prgm 2 data 2 2 master ending address 1 master ending address 2 master ending address 3 master ending address 4 master address translation address 4 vmechip2 lcsr base address = $base + 0000 offset: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mast d16 en mast wp en mast d16 en mast wp en master am 3 master am 4 gcsr group select gcsr board select mast 4 en mast 3 en mast 2 en mast 1 en tick 2/1 tick irq 1 en clr irq irq stat vmebus interrupt level vmebus interrupt vector 0 4 8 c 10 14 18 1c 20 24 28 2c 30 34 38 3c 40 44 48 wait rmw dma controller dma controller dma controller dma controller this sheet continues on facing page. .com .com .com .com .com 4 .com u datasheet
operating instructions 2-13 2 arb robn mast dhb mast dwb mst fair mst rwd master vmebus dma halt dma en dma tbl dma fair dm relm dma vmebus adder 1 mast wp en mast wp en mast d16 en mast d16 en snp 1 wp 1 sup 1 usr 1 a32 1 a24 1 blk 1 prgm 1 data 1 blk d64 1 master starting address 1 master starting address 2 master starting address 3 master starting address 4 master address translation select 4 slave starting address 1 slave starting address 2 slave address translation select 1 slave address translation select 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 io2 en io2 wp en io2 s/u io2 p/d io1 en io1 d16 en io1 wp en io1 s/u 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 master am 2 master am 1 rom size rom bank b speed rom bank a speed dma tbl int dma lb snp mode dma inc vme dma inc lb dma d64 blk dma blk dma am 5 dma am 4 dma wrt dma d16 dma am 3 dma am 2 dma am 1 dma am 0 dma table interrupt count mpu clr stat mpu lbe err mpu lpe err mpu lob err mpu lto err dma lbe err dma lpe err dma lob err dma lto err dma tbl err dma vme err dma done local bus address counter vmebus address counter byte counter table address counter 1360 9403 this sheet begins on facing page. .com .com .com .com .com 4 .com u datasheet
memory maps 2-14 2 table 2-6. vmechip2 memory map (sheet 2 of 3) en irq 31 en irq 30 en irq 29 en irq 28 en irq 27 en irq 26 en irq 25 en irq 24 en irq 23 en irq 22 en irq 21 en irq 20 en irq 19 en irq 18 en irq 17 en irq 16 clr irq 31 clr irq 30 clr irq 29 clr irq 28 clr irq 27 clr irq 26 clr irq 25 clr irq 24 clr irq 23 clr irq 22 clr irq 21 clr irq 20 clr irq 19 clr irq 18 clr irq 17 clr irq 16 ac fail irq level vmechip2 lcsr base address = $base + 0000 offset: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 68 6c 70 74 78 7c 80 84 88 8c ac fail irq ab irq sys fail irq mwp berr irq pe irq irq1e irq tic2 irq tic1 irq vme iack irq dma irq sig3 irq sig2 irq sig1 irq sig0 irq lm1 irq lm0 irq abort irq level sys fail irq level mst wp error irq level vme iack irq level dma irq level sig 3 irq level sig 2 irq level sw7 irq level sw6 irq level sw5 irq level sw4 irq level spare irq level vme irq 7 irq level vme irq 6 irq level vme irq 5 irq level vector base register 0 vector base register 1 mst irq en sys fail level ac fail level abort level gpioen 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 arb bgto en dma time off dma time on vme global timer sys fail scon brd fail stat purs stat clr purs stat brd fail out rst sw en sys rst wd clr to wd clr cnt wd to stat to bf en wd srst lrst wd rst en wd en pre 4c 50 54 58 5c 60 64 tick timer 1 tick timer 1 tick timer 2 tick timer 2 this sheet continues on facing page. .com .com .com .com .com 4 .com u datasheet
operating instructions 2-15 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vme access timer local bus timer wd time out select prescaler clock adjust tic en 1 coc en 1 clr ovf 1 tic en 2 coc en 2 clr ovf 2 overflow counter 1 overflow counter 2 scaler 1361 9403 compare register counter compare register counter en irq 15 en irq 14 en irq 13 en irq 12 en irq 11 en irq 10 en irq 9 en irq 8 en irq 7 en irq 6 en irq 5 en irq 4 en irq 3 en irq 2 en irq 1 en irq 0 clr irq 15 clr irq 14 clr irq 13 clr irq 12 clr irq 11 clr irq 10 clr irq 9 clr irq 8 set irq 15 set irq 14 set irq 13 set irq 12 set irq 11 set irq 10 set irq 9 set irq 8 sw7 irq sw6 irq sw5 irq sw4 irq sw3 irq sw2 irq sw1 irq sw0 irq spare vme irq7 vme irq6 vme irq5 vme irq4 vme irq3 vme irq2 vme irq1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioo p error irq level irq1e irq level tic timer 2 irq level tic timer 1 irq level sw3 irq level sw2 irq level sw1 irq level sw0 irq level vme irq 4 irq level vmeb irq 3 irq level vme irq 2 irq level vme irq 1 irq level sig 1 irq level sig 0 irq level lm 1 irq level lm 0 irq level gpioi gpi mp irq en rev erom no el bbsy dis sram dis mst dis bsyt en int dis bgn this sheet begins on facing page. .com .com .com .com .com 4 .com u datasheet
programming considerations 2-16 2 table 2-6. vmechip2 memory map (sheet 3 of 3) programming considerations good programming practice dictates that only one mpu at a time have control of the MVME1603/1604 control registers. of particular note are: o registers that modify the address map o registers that require two cycles to access o vmebus interrupt request registers vmechip2 gcsr base address = $base + 0100 offsets vme- bus local bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 chip revision chip id 24 lm3 lm2 lm1 lm0 sig3 sig2 sig1 sig0 rst isf bf scon sysfl xxx 48 general purpose control and status register 0 6c general purpose control and status register 1 810 general purpose control and status register 2 a14 general purpose control and status register 3 c18 general purpose control and status register 4 e1c general purpose control and status register 5 .com .com .com .com .com 4 .com u datasheet
operating instructions 2-17 2 pci arbitration there are 6 potential pci bus masters on the MVME1603/mvme1604 single-board computer: o mpc105 (pci/mpu bus bridge and memory controller) o ibc (pci/isa bus bridge controller) o decchip 21040 ethernet controller o 53c825 (or 53c810) scsi controller o vme2pci asic (pci/vmechip2 interface asic o pmc (pci mezzanine card) slot the ibc supplies the pci arbitration support for these six devices. the ibc supports flexible arbitration modes of fixed priority, rotating priority, and mixed priority. the ibc registers that control the arbitration mode are the pci arbiter priority control (papc) register and the pci arbiter priority control extension (arbprix) register. the papc register and the arbprix register default to 04 (hex) and 00 (hex) respectively. this default configuration puts the cpu (mpc105) at the highest priority level. refer to the s82378zb reference manual for programming information. the following figure shows the arbitration configuration diagram of the ibc. additional details on pci arbitration can be found in the programmers reference guide (part number v1600-1a/pg). .com .com .com .com .com 4 .com u datasheet
programming considerations 2-18 2 figure 2-1. ibc arbiter configuration diagram the pci arbitration assignments for all pci masters on the MVME1603/mvme1604 are as follows: table 2-7. pci arbitration assignments pci bus request cpureq * ibcreq * req0 * req1 * req2 * req3 * pci master cpu (mpc105) ibc (internal) scsi (53c825) lanc (decchip 21040) vme (vme2pci) pmc slot bank 0 11187.00 9411 bank 3 bank 1 ibcreq * (internal to ibc) req0 * 0 1 0 1 0 1 fixed control bank 0 rotate control bank 0 fixed control bank 3 rotate control bank 3 fixed control bank 1 rotate control bank 1 req1 * req2 * cpureq * req3 * 00 01 10 bank 2 fixed control bank 2 a fixed control bank 2 b rotated control bank 2 .com .com .com .com .com 4 .com u datasheet
operating instructions 2-19 2 interrupt handling the MVME1603/mvme1604 supports both maskable and non-maskable interrupts. the following figure illustrates the interrupt architecture. figure 2-2. MVME1603/mvme1604 interrupt architecture 11188.00 9411 int * int ibc mpc603 or mpc604 nmi mpc105 mcp * serr * & perr * pci interrupts isa interrupts host connectors .com .com .com .com .com 4 .com u datasheet
programming considerations 2-20 2 machine check interrupt (mcp * ) the ibc can be programmed to assert nmi when it detects either serr * low on the pci local bus or iochk * low on the isa bus. however, iochk * is not used on the MVME1603/mvme1604. the mpc105 will assert mcp * to the processor upon detecting a high level on nmi from the ibc. note that mpc105 also monitors serr * and perr * . it can be programmed to asserted mcp * when it detects a low level on either serr * or perr * . the mpc105 can also be programmed to assert mcp * under many other conditions. refer to the programmers reference guide (part number v1600-1a/pg) for additional information on the mcp * interrupt signal. maskable interrupts the ibc supports 15 interrupt requests. these 15 interrupts are isa-type interrupts that are functionally equivalent to two 82c59 interrupt controllers. except for irq0, irq1, irq2, irq8 * , and irq13, each of the interrupt lines can be configured for either edge-sensitive or level-sensitive mode by programming the appropriate elcr registers in the ibc. the ibc also supports four pci interrupts: int3 * -int0 * . the ibc has four pirq route control registers to allow each pci interrupt line to be routed to any of eleven isa interrupt lines (irq0, irq1, irq2, irq8 * , and irq13 are reserved for isa system interrupts). since pci interrupts are defined as level-sensitive, software must program the selected irq(s) for level-sensitive mode. note that more than one pci interrupt can be routed to the same isa irq line. the following figure shows the ibc interrupt structure. additional details on interrupt assignments can be found in the programmers reference guide (part number v1600-1a/pg). .com .com .com .com .com 4 .com u datasheet
operating instructions 2-21 2 figure 2-3. ibc interrupt handler block diagram 11189.00 9411 pirq route control register pirq0 * irqx pirq route control register pirq1 * irqx pirq route control register pirq2 * irqx pirq route control register pirq3 * irqx controller 1 (int1) timer1/counter0 0 1 2 3 4 5 6 7 irq1 irq3 irq4 irq5 irq6 irq7 controller 2 (int2) irq8 0 1 2 3 4 5 6 7 irq9 irq11 irq12 irq13 irq14 irq15 intr irq10 .com .com .com .com .com 4 .com u datasheet
programming considerations 2-22 2 vmechip2 interrupts vmechip2 interrupts consist of interrupts from the vmebus irq lines and from the vmechip2 internal resources (i.e., dma and timers). you can program the vmechip2 interrupt control registers as though the system were mc68040-based (i.e., with interrupt priority levels from 1 through 7). when an interrupt is pending, the vmechip2 asserts three encoded interrupt request lines (ipl2 * -ipl0 * ) to the vme2pci device. an interrupt is then issued by the vme2pci device to the processor through the ibc. after learning from the ibc that the source of the interrupt is the vme2pci, the software determines the interrupt level to acknowledge the vmechip2 by examining the ilvl status bits of the interrupt control and status register in the vme2pci asic. finally, to get the interrupt vector from the vmechip2, the interrupt handling routine must read the appropriate pseudo iack registers. z8536 and z85230 interrupts after learning from the ibc that the source of the interrupt is the z85230/z8536 devices, the software can either poll the two devices or perform an 8-bit read access to the z85230/z8536 pseudo iack register to get the interrupt vector. refer to the z85230 and the z8536 data sheets for programming information and additional information about their interrupt structures. abt (abort) interrupt the MVME1603/mvme1604 can be programmed to generate an interrupt to the processor via isa interrupt irq8 * when the abort switch is activated (refer also to the abort switch section at the beginning of this chapter). the abort * signal is also routed to pin pb7 of the z8536 device. refer to the 82c378zb and the z8536 data sheets for programming information. .com .com .com .com .com 4 .com u datasheet
operating instructions 2-23 2 dma channels the ibc supports seven dma channels. these dma channels are allocated as follows: sources of reset the MVME1603/mvme1604 sbc has six equally powerful potential sources of reset: 1. power-on reset 2. reset switch 3. alt_rst * function controlled by the port 92 register in the ibc (resets the vmebus when the MVME1603/mvme1604 is system controller) 4. keyboard reset function from the keyboard controller in the isasio (isa super i/o) device 5. reset sources from the vmechip2: the vmebus sysreset * , watchdog reset, and software reset functions. table 2-8. ibc dma channel assignments ibc priority ibc label controller dma assignment dma request polarity 1 channel 0 dma1 serial port 3 receiver (z85230 port a rx) high 2 channel 1 serial port 3 transmitter (z85230 port a tx) high 3 channel 2 reserved for floppy drive controller high 4 channel 3 parallel port high 5 channel 4 dma2 not available - cascaded from dma1 n/a 6 channel 5 serial port 4 receiver (z85230 port b rx) high 7 channel 6 serial port 4 transmitter (z85230 port b tx) high 8 channel 7 not used high .com .com .com .com .com 4 .com u datasheet
programming considerations 2-24 2 6. when the MVME1603/mvme1604 is operating as the vmebus system controller, an hreset * signal will also cause a vmebus sysreset * . endian issues the MVME1603/mvme1604 supports both little-endian (e.g. windows nt) and big-endian software (e.g. aix). the powerpc processor and the vmebus are inherently big-endian, while the pci bus is inherently little- endian. the following figures illustrate how the MVME1603/mvme1604 handles the endian issue in big-endian and little-endian modes: processor/memory domain the mpc603/604 processor can operate in both big-endian and little- endian mode. however, it always treats the external processor/memory bus as big-endian by performing address rearrangement and reordering when running in little-endian mode. role of the mpc105 because the pci bus is little-endian, the mpc105 performs byte swapping in both directions (from pci to memory and from the processor to pci) to maintain address invariance while programmed to operate in big-endian mode with the processor and the memory subsystem. in little-endian mode, the mpc105 reverse-rearranges the address for pci-bound accesses and rearranges the address for memory-bound accesses (from pci). in this case, no byte swapping is done. .com .com .com .com .com 4 .com u datasheet
operating instructions 2-25 2 figure 2-4. big-endian mode n-way byte swap vmechip2 mpc105 vme2pci big endian little endian little endian big endian pci vmebus dram n-way byte swap 11190.00 9411 big-endian program .com .com .com .com .com 4 .com u datasheet
programming considerations 2-26 2 figure 2-5. little-endian mode 11191.00 9411 n-way byte swap vmechip2 mpc105 vme2pci big endian little endian little endian big endian pci vmebus dram ea modification little endian big endian ea modification (xor) little-endian program .com .com .com .com .com 4 .com u datasheet
operating instructions 2-27 2 pci domain the pci bus is inherently little-endian and all devices connected directly to pci will operate in little-endian mode, regardless of the mode of operation in the processors domain. 53c825 or 53c810(scsi) scsi is byte-stream-oriented; the byte having the lowest address in memory is the first one to be transferred regardless of the endian mode. since the mpc105 maintains address invariance in both little-endian and big-endian mode, there should be no endian issues for the scsi data. big- endian software must still be aware of the byte-swapping effect when accessing the registers of the 53c825 or 53c810, however. dec21040 (ethernet) ethernet is also byte-stream-oriented; the byte having the lowest address in memory is the first one to be transferred regardless of the endian mode. since the mpc105 maintains address invariance in both little-endian and big-endian mode, there should be no endian issues for the ethernet data. big-endian software must still be aware of the byte-swapping effect when accessing the registers of the dec21040, however. gd5446 (graphics) big-endian graphic software must take the effects of byte-swapping on big-endian software into account. role of the vme2pci because pci is little-endian and the vmebus is big-endian, the vme2pci performs byte swapping in both directions (from pci to vmebus and from vmebus to pci) to maintain address invariance, regardless of the mode of operation in the processors domain. vmebus domain the vmebus is inherently big-endian. all devices connected directly to the vmebus are expected to operate in big-endian mode, regardless of the mode of operation in the processors domain. .com .com .com .com .com 4 .com u datasheet
programming considerations 2-28 2 in big-endian mode, byte-swapping is performed first by the vme2pci and then by the mpc105. the result has the desirable effect of being transparent to the big-endian software. in little-endian mode, however, software must take the byte-swapping effect of the vme2pci and the address reverse-rearranging effect of the mpc105 into account. .com .com .com .com .com 4 .com u datasheet
3 3-1 3 functional description introduction this chapter describes the MVME1603/mvme1604 single-board computer on a block diagram level. the general description provides an overview of the MVME1603/mvme1604, followed by a detailed description of several blocks of circuitry. figure 3-1 shows a block diagram of the overall board architecture. detailed descriptions of other MVME1603/mvme1604 blocks, including programmable registers in the asics and peripheral chips, can be found in the programmers reference guide (part number v1600-1a/pg). refer to it for a functional description of the MVME1603/mvme1604 in greater depth. features the following table summarizes the features of the mvme1600-001- and mvme1600-011-based MVME1603/mvme1604 single-board computers. table 3-1. MVME1603/mvme1604 features feature description models microprocessor mpc603 powerpc tm processor MVME1603 mpc604 powerpc tm processor mvme1604 (2 slots) dram up to 64mb on processor module all models 8mb-64mb on ram104 module (192mb available as factory order only) all models l2 cache memory (optional) 256kb on processor module pm603-02 x , pm604-01 x boot rom two 32-pin plcc sockets (1mb flash) all models software-readable header 8-bit readable header (4 bits reserved for firmware, 4 bits user-definable) all models .com .com .com .com .com 4 .com u datasheet
features 3-2 3 real-time clock 8kb nvram with rtc and battery backup (sgs-thomson m48t18) all models switches reset and abort all models status leds six: chs , bfl , cpu , pci , fus , and sys all models tick timers four programmable 16-bit timers (one in s82378zb isa bridge; three in z8536 cio device) all models watchdog timer provided in vmechip2 all models interrupts eight software interrupts all models vme i/o vmebus p2 connector all models serial i/o 2 async ports, 2 sync/async ports via p2 and mvme760 transition module (async: pc87303 sio; sync: zilog 85230 escc) mvme1600-001 base board 2 async ports via p2 and mvme712m transition module; 2 sync/async ports via p2 and mvme712m or front panel mvme1600-011 base board parallel i/o ieee1284 bidirectional parallel port (pc87303 sio) via p2 and transition module all models scsi i/o 16-bit scsi interface (ncr 53c825) via front panel mvme1600-001 base board 8-bit scsi interface (ncr 53c810) via p2 and mvme712m transition module mvme1600-011 base board ethernet i/o aui and 10baset connections via p2 and mvme760 transition module mvme1600-001 base board aui connection via p2 and mvme712m transition module; 10baset connection via front panel mvme1600-011 base board pci interface one ieee p1386.1 pci mezzanine card (pmc) slot all models keyboard/mouse interface support for keyboard and mouse input (pc87303 sio) via front panel mvme1600-001 base board graphics port super vga high-resolution color graphics (cl-gd5446 graphics accelerator) mvme1600-001 base board table 3-1. MVME1603/mvme1604 features (continued) feature description models .com .com .com .com .com 4 .com u datasheet
functional description 3-3 3 general description the MVME1603/1604 is a vmemodule single-board computer equipped with a powerpc? series microprocessor. the MVME1603 is equipped with a powerpc 603 microprocessor; the mvme1604 has a powerpc 604. 256kb l2 cache memory is available as an option on certain models of the MVME1603 and the mvme1604. the MVME1603/1604 family has two parallel branches based on two distinct versions (mvme1600-001 and mvme1600-011) of the base board. the differences between the mvme1600-001 and the mvme1600-011 lie mainly in the area of i/o handling; the logic design is the same for both versions. as shown in the features section, the MVME1603/mvme1604 offers many standard features desirable in a computer systemsuch as synchronous and asynchronous serial ports, parallel port, boot rom and dram, scsi, ethernet, provision for a disk drive mezzanine, and (mvme1600-001 base board only) keyboard, mouse, and graphics floppy disk controller support for floppy disk drive (pc87303 sio) via connectors on base board all models vmebus interface vmebus system controller functions all models vmebus-to-local-bus interface (a24/a32, d8/d16/d32/block transfer [d8/d16/d32/d64]) local-bus-to-vmebus interface (a16/a24/a32, d8/d16/d32) vmebus interrupter vmebus interrupt handler global csr for interprocessor communications dma for fast local memory/vmebus transfers (a16/a24/a32, d16/d32/d64) table 3-1. MVME1603/mvme1604 features (continued) feature description models .com .com .com .com .com 4 .com u datasheet
block diagram 3-4 3 supportin a one- or two-slot vme package. its flexible mezzanine architecture allows relatively easy upgrades of the processor and/or memory. a key feature of the MVME1603/mvme1604 family is the pci (peripheral component interconnect) bus. in addition to the on-board local bus peripherals, the pci bus supports an industry-standard mezzanine interface, ieee p1386.1 pmc (pci mezzanine card). pmc modules offer a variety of possibilities for i/o expansion through fddi (fiber distributed data interface), atm (asynchronous transfer mode), graphics, ethernet, or scsi ports. both base boards support pmc front panel i/o. block diagram figure 3-1 is a block diagram of the MVME1603/mvme1604s overall architecture. shaded areas of the diagram apply to mvme1600-001-based versions only. .com .com .com .com .com 4 .com u datasheet
functional description 3-5 3 figure 3-1. MVME1603/mvme1604 block diagram vme2pci rtc/ nvram ram104 pm603/pm604 mpu/dram module mpc603/604 dram dram rom buffers vme vmechip2 scsi ncr-53c8xx ethernet decchip vga cl-gd5446 32-bit pci local bus pci expansion pmc slot mvme1600-001 / 011 base board mouse keyboard serial parallel i/o notes : 1. shaded boxes are mvme1600-001 features only. 2. scsi controller is ncr-53c825 on mvme1600-001, ncr-53c810 on -011. floppy disk controller video ram 21040 l2 cache (optional) mpc105 isa bridge 11186.00 9606 .com .com .com .com .com 4 .com u datasheet
block diagram 3-6 3 scsi interface the MVME1603/mvme1604 supports mass storage subsystems through the industry-standard scsi bus. these subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices. the scsi interface is implemented using the ncr 53c825 (on the mvme1600-001 base board) or ncr 53c810 (on the mvme1600-011 base board) scsi i/o controller at a clock speed of 40mhz. the scsi i/o controller connects directly to the pci local bus. the mvme1600-001 base board has an industry-standard 68-pin high- density scsi connector on the front panel (as illustrated in figure 1-3). the mvme1600-011 base board routes its scsi lines through the p2 connector to the mvme712m transition module (as illustrated in figure 1-13). the scsi control lines have filter networks to minimize the effects of vmebus signal noise at p2. the scsi bus is 16 bits wide in mvme1600-001-based versions of the MVME1603/mvme1604, and 8 bits wide in mvme1600-011-based versions. refer to chapter 4 for the pin assignments of the mvme1600- 001 front panel scsi connector. refer to the mvme712m user's manual for the pin assignments of the transition module scsi connectors used in the mvme1600-011 scsi implementation. refer to the ncr 53c825 and 53c810 user's guides and the MVME1603/mvme1604 programmer's reference guide for detailed programming information. scsi termination the individual configuring the system must ensure that the scsi bus is properly terminated at both ends. the mvme1600-001 base board provides onboard scsi bus termination. the terminators can be enabled or disabled by a jumper (j7described in chapter 1). if the scsi bus ends at the MVME1603/mvme1604 module, then scsi termination must be enabled. +5vdc power to the scsi bus termpwr signal and termination resistors is supplied through a fuse (f1) and diode. .com .com .com .com .com 4 .com u datasheet
functional description 3-7 3 the mvme1600-011 base board uses the sockets provided for scsi bus terminators on the p2 adapter board. if the scsi bus ends at the adapter board, then termination resistors must be installed on the adapter board. +5vdc power to the scsi bus termpwr signal and termination resistors is supplied through a fuse located on the adapter board. ethernet interface the MVME1603/mvme1604 uses digital equipments decchip 21040 lan controller to implement an ethernet interface that supports both aui and 10baset connections. the balanced differential transceiver lines for aui and 10baset are coupled via on-board transformers. the mvme1600-001 base board routes its aui and 10baset lines through the p2 connector to the mvme760 transition module (as illustrated in figure 1-12 on page 1-41). the mvme760 front panel has an industry-standard db15 connector and 8-pin rj45 connector for the aui and 10baset connections respectively (see figure 1-4 on page 1-17). the mvme1600-011 base board uses an 8-pin rj45 on its front panel for 10baset lines (see figure 1-5 on page 1-19) and routes its aui lines through the p2 connector to the mvme712m transition module (as illustrated in figure 1-13 on page 1-44). the mvme712m front panel has an industry-standard db15 connector for the aui connections (see figure 1-6 on page 1-28). every MVME1603/mvme1604 is assigned an ethernet station address. the address is $08003e2 xxxxx , where xxxxx is the unique 5-nibble number assigned to the board (i.e., every board has a different value for xxxxx ). each MVME1603/mvme1604 displays its ethernet station address on a label attached to backplane connector p2. in addition, the six bytes including the ethernet station address are stored in the nvram (bbram) configuration area specified by boot rom. that is, 08003e2 xxxxx is stored in nvram. at an address of $fffc1f2c, the upper four bytes (08003e2 x ) can be read. at an address of $fffc1f30, the lower two bytes ( xxxx ) can be read. the MVME1603/mvme1604 debugger, ppcbug, has the capability to retrieve or set the ethernet station address. .com .com .com .com .com 4 .com u datasheet
block diagram 3-8 3 if the data in the nvram is lost, use the number on the label on backplane connector p2 to restore it. refer to chapter 4 for the pin assignments of the mvme1600-011 front panel 10baset connector. refer to the mvme712m user's manual for the pin assignments of the transition module aui connector. refer to the mvme760 user's manual for the pin assignments of the transition module aui and 10baset connectors used in the mvme1600-001 ethernet implementation. refer to the bbram/tod clock memory map description in the MVME1603/mvme1604 programmer's reference guide for detailed programming information. note the MVME1603/mvme1604 will support either aui or 10baset ethernet connections, but not both at the same time. to switch from one type to the other, do the following: 1. bring the MVME1603/mvme1604 up in ppcbug. 2. remove the current ethernet cable and connect the one you wish to use. 3. reset the MVME1603/mvme1604 by pressing the reset switch or typing the debug command reset . the new connection is automatically recognized by the lan controller. graphics interface mvme1600-001-based versions of the MVME1603/mvme1604 have a super vga (video graphics array) color graphics interface implemented with a cirrus logic cl-gd5446 graphics accelerator. the cl-gd5446 supports pixel clock rates of up to 110mhz. its internal palette dac is configurable for industry-standard 16- or 256-color vga modes. the dac is also extensible to high- and true-color modes of 32 thousand or 16.7 million colors. depending on the color selection and bits-per-pixel mode, the cl-gd5446 device supports resolutions of up to 1280 x 1024. 2mb of video buffer memory (in the form of four 256k x 16, 40-pin soj, 60ns dram chips) are available to the cl-gd5446. .com .com .com .com .com 4 .com u datasheet
functional description 3-9 3 the vga port routes the graphics data to an industry-standard 3-row db15 connector on the front panel of the mvme1600-001 base board (as illustrated in figure 1-3). refer to chapter 4 for the pin assignments of the mvme1600-001 front panel vga connector. refer to cirrus logics cl-gd5446 technical reference manual for detailed programming information. pci mezzanine interface a key feature of the MVME1603/mvme1604 family is the pci (peripheral component interconnect) bus. in addition to the on-board local bus devices (scsi, ethernet, graphics, etc.), the pci bus supports an industry-standard mezzanine interface, ieee p1386.1 pmc (pci mezzanine card). pmc modules offer a variety of possibilities for i/o expansion through fddi (fiber distributed data interface), atm (asynchronous transfer mode), graphics, ethernet, or scsi ports. both versions of the base board support pci front panel i/o. the MVME1603/mvme1604 supports one pmc slot. two 64-pin connectors on the base board (j11 and j12) interface with 32-bit ieee p1386.1 pmc-compatible mezzanines to add any desirable function. the pci mezzanine card slot has the following characteristics: refer to chapter 4 for the pin assignments of the pmc connectors. for detailed programming information, refer to the pci bus descriptions in the MVME1603/mvme1604 programmer's reference guide and to the user documentation for the pmc modules you intend to use. mezzanine type pmc (pci mezzanine card) mezzanine size s1b: single width, standard depth (75mm x 150mm) with front panel pmc connectors j11 and j12 (32-bit pci with front-panel i/o only) signaling voltage v io = 5.0vdc .com .com .com .com .com 4 .com u datasheet
block diagram 3-10 3 vmebus interface the vmechip2 asic, in tandem with the vme2pci asic, constitutes the vmebus interface. the vmechip2 interfaces an mc68040-style local bus to the vmebus. the vme2pci interfaces the pci bus to an mc68040- style local bus. when the vmechip2 and the vme2pci chips are used together, they form a pci-bus-to-vmebus interface. the vmechip2/vme2pci combination provides: o the local-bus-to-vmebus interface o the vmebus-to-local-bus interface o the dma controller functions of the local vmebus the vmechip2 includes global control and status registers (gcsrs) for interprocessor communications. it can provide the vmebus system controller functions as well. for detailed programming information, refer to the vmechip2 and vme2pci discussions in the MVME1603/mvme1604 programmer's reference guide . isa super i/o device (isasio) the MVME1603/mvme1604 uses a pc87303 isasio chip from national semiconductor to implement certain segments of the p2 and front-panel i/o: o two asynchronous serial ports (com1 and com2) via p2 and transition module o ieee1284 bidirectional parallel port via p2 and transition module o disk drive support via drive connector j6 and power connector j16 (on the mvme1600-001) or j19 (on the mvme1600-011) o keyboard and mouse interface (mvme1600-001 base board only) asynchronous serial ports the two asynchronous ports provided by the isasio device employ ttl- level signals that are routed to the p2 connector. the ttl output lines are buffered through ttl drivers and series resistors. the eia-232-d drivers and receivers that complete the serial interface are located on the mvme760 (for the mvme1600-001 base board) or mvme712m (for the mvme1600-011 base board) transition module. .com .com .com .com .com 4 .com u datasheet
functional description 3-11 3 hardware initializes the two serial ports as com1 and com2 with isa i/o base addresses of $3f8 and $2f8 respectively. this default configuration also assigns com1 to ibc (isa/pci bridge controller) interrupt request line irq4 and com2 to irq3. you can change the default configuration by reprogramming the isasio device. for detailed programming information, refer to the pci and isa bus discussions in the MVME1603/mvme1604 programmer's reference guide and to the vendor documentation for the isasio device. parallel port the parallel port is an ieee p1284 printer interface implemented with the isasio device. all parallel i/o interface signals are routed to p2 through series damping resistors. hardware initializes the parallel port as ppt1 with an isa io base address of $3bc. this default configuration also assigns the parallel port to ibc (isa/pci bridge controller) interrupt request line irq7. you can change the default configuration by reprogramming the isasio device. for detailed programming information, refer to the pci and isa bus discussions in the MVME1603/mvme1604 programmer's reference guide and to the vendor documentation for the isasio device. .com .com .com .com .com 4 .com u datasheet
block diagram 3-12 3 disk drive controller the isasio device incorporates a low- and high-density disk drive controller for use with an optional disk drive. the disk drive may take the form of a mezzanine board or a separate module. the drive interfaces with the isasio controller via base board connector j6. the unit receives power via connector j16 (on the mvme1600-001) or j19 (on the mvme1600-011). the isasio disk drive controller is compatible with the dp8473, 765a, and n82077 devices commonly used to implement floppy disk controllers. software written for those devices may be used without change to operate the isasio controller. the isasio device may be used to support any of the following devices: o 3 1 / 2 -inch 1.44mb floppy disk drive o 5 1 / 4 -inch 1.2mb floppy disk drive o standard 250kbps to 2mbps tape drive system keyboard and mouse interface on the mvme1600-001 base board, the isasio device provides rom- based keyboard and mouse interface control. the front panel of the mvme1600-001 board has two 6-pin circular din connectors for keyboard and the mouse connections. isa bridge controller the MVME1603/mvme1604 uses an intel s82378zb bridge controller to supply the interface between the pci local bus and the isa system i/o bus (diagrammed in figure 1-1 and figure 1-2 for the two base boards). .com .com .com .com .com 4 .com u datasheet
functional description 3-13 3 the isa bridge controller provides the following functions: o pci bus arbitration for: C the mpc105 (pci/mpu bus bridge and memory controller) C the scsi controller C the ethernet controller C the vme2pci asic C the pmc (pci mezzanine card) slot o isa bus arbitration for dma devices o isa interrupt mapping for four pci interrupts o interrupt controller functionality to support 14 isa interrupts o edge/level control for isa interrupts o seven independently programmable dma channels o one 16-bit timer o three interval counters/timers the base address of the configuration space for the isa bridge controller is at $00800800 in the pci configuration area. real-time clock and nvram the MVME1603/mvme1604 employs an sgs-thomson surface-mount m48t18 ram and clock chip to provide 8kb of non-volatile static ram and a real-time clock. this chip provides a clock, oscillator, crystal, power failure detection, memory write protection, 8kb of nvram, and a battery in a package consisting of two parts: o a 28-pin 330mil so device containing the real-time clock, the oscillator, power failure detection circuitry, 8kb of sram, and gold-plated sockets for a snaphat battery o a snaphat battery housing a crystal along with the battery .com .com .com .com .com 4 .com u datasheet
block diagram 3-14 3 the snaphat battery package is mounted on top of the mt48t18 device. the battery housing is keyed to prevent reverse insertion. the clock furnishes seconds, minutes, hours, day, date, month, and year in bcd 24-hour format. corrections for 28-, 29- (leap year), and 30-day months are made automatically. the clock generates no interrupts. although the m48t18 is an 8-bit device, 8-, 16-, and 32-bit accesses from the isa bus to the m48t18 are supported. refer to the MVME1603/mvme1604 programmer's reference guide and to the m48t18 data sheet for detailed programming and battery life information. programmable timers among the resources available to the local processor are a number of programmable timers. timers are incorporated into the isa bridge controller, the z8536 cio device (diagrammed in figure 1-1 and figure 1- 2 for the two base boards), and the vmechip2. they can be programmed to generate periodic interrupts to the processor. interval timers the isa bridge controller has three built-in counters that are equivalent to those found in an 82c54 programmable interval timer. these counters are grouped into one timer unit, timer 1, in the ibc. each counter output has a specific function: o counter 0 is associated with interrupt request line irq0. it can be used for system timing functions, such as timer interrupt for a time- of-day. o counter 1 generates a refresh request signal for isa memory. this timer is not used in the MVME1603/mvme1604. o counter 2 provides the tone for the speaker output function on the isa bridge controller (the speaker_out signal which can be cabled to an external speaker via the remote reset connector). the interval timers use the osc clock input as their clock source. the MVME1603/mvme1604 module drives the osc pin with a 14.31818 mhz clock source. .com .com .com .com .com 4 .com u datasheet
functional description 3-15 3 16-bit timers four 16-bit timers are available on the MVME1603/mvme1604. the isa bridge controller supplies one 16-bit timer; the z8536 cio device provides the other three. for information on programming these timers, refer to the data sheets for the s82378zb isa bridge controller and the z8536 cio device. vmechip2 timers two 32-bit programmable tick timers are available in the optional vmechip2 asic. refer to the vmechip2 description in the MVME1603/mvme1604 programmer's reference guide for detailed programming information. note it is advisable to avoid using these timers for system timing functions, since the vmechip2 may not be present in all versions of the MVME1603/mvme1604 module. serial communications interface the MVME1603/mvme1604 uses a zilog z85230 escc (enhanced serial communications controller) to implement the two synchronous/asynchronous serial communications interfaces, which are routed through p2 for the mvme1600-001 base board and through the front panel for the mvme1600-011 base board. the z85230 supports synchronous (sdlc/hdlc) and asynchronous protocols. the MVME1603/mvme1604 hardware supports asynchronous serial baud rates of 110b/s to 38.4kb/s. each interface supports the cts, dcd, rts, and dtr control signals as well as the txd and rxd transmit/receive data signals, and txc/rxc synchronous clock signals. since not all modem control lines are available in the z85230, a z8536 cio is used to provide the missing modem lines. .com .com .com .com .com 4 .com u datasheet
block diagram 3-16 3 in the mvme1600-001 base board, all modem control lines from the escc are multiplexed/demultiplexed through p2 by a multiplexing function (p2mx, described later in this chapter) due to the pin limitations of the p2 connector. a pal device performs decoding of register accesses and pseudo interrupt acknowledge cycles for the z85230 and the z8536 in isa i/o space. the isa bridge controller supplies dma support for the z85230. the z85230 receives a 10mhz clock input. the z85230 supplies an interrupt vector during pseudo interrupt acknowledge cycles. the vector is modified within the z85230 according to the interrupt source. interrupt request levels are programmed via the isa bridge controller. refer to the z85230 data sheet and to the MVME1603/ mvme1604 programmer's reference guide for further information. z8536 cio device the z8536 cio device complements the z85230 escc by supplying signals for abort interrupt status, fuse status, and scsi terminator status and control, as well as furnishing modem control lines not provided by the z85230 escc. in addition, the z8536 cio device has three independent 16-bit counters/timers. for mvme1600-001 base boards, the z8536 cio device also provides a means of requesting the module id of the two synchronous/asynchronous serial ports that reside on the mvme760 transition module. refer to the z8536 data sheet and to the MVME1603/mvme1604 programmer's reference guide for further information. board configuration register the board configuration register is an 8-bit read-only register containing the details of the MVME1603/mvme1604 single-board computers configuration. this register is located on the base board at isa i/o address $0802. board configuration register - $0802 bit sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 .com .com .com .com .com 4 .com u datasheet
functional description 3-17 3 giop * transition module present. if set, the mvme760 transition module is not connected. if cleared, the mvme760 module is connected. ( mvme1600-001 base boards only; not applicable to mvme1600-011 boards.) sccp * z85230 escc present. if set, there is no on-board synchronous serial support (the escc not present). if cleared, the z85230 escc is installed and there is on-board support for synchronous serial communication. pmcp * pmc present. if set, no pci mezzanine card is installed in the pmc slot. if cleared, the pmc slot contains a pci mezzanine card. vmep * vmebus present. if set, there is no vmebus interface. if cleared, the vmebus interface is supported. gfxp * graphics present. if set, no graphics interface is installed. if cleared, onboard graphics are available (mvme1600-001 base board only; the mvme1600-011 has no graphics capability). lanp * ethernet present. if set, no ethernet transceiver interface is installed. if cleared, there is on-board ethernet support. scsip * scsi present. if set, there is no on-board scsi interface. if cleared, on-board scsi is supported. p2 signal multiplexing due to the limited availability of pins in the p2 backplane connector, the mvme1600-001 base board multiplexes and demultiplexes certain synchronous i/o control signals that pass between the base board and the mvme760 transition module. this is a hardware function that is entirely transparent to software. field giop * sccp * pmcp * vmep * gfxp * lanp * scsip * oper rrrrrrrr reset n/a n/a 1 n/a n/a n/a n/a n/a board configuration register - $0802 .com .com .com .com .com 4 .com u datasheet
block diagram 3-18 3 four signals are involved in the p2 multiplexing function: mxdo, mxdi, mxclk, and mxsync * . mxdo is a time-multiplexed data output line from the main board and mxdi is a time-multiplexed line from the mvme760 module. mxclk is a 10mhz bit clock for the mxdo and mxdi data lines. mxsync * is asserted for one bit time at time slot 15 (refer to the following table) by the mvme1600-001 base board. the mvme760 transition module uses mxsync * to synchronize with the base board. a 16-to-1 multiplexing scheme is used with mxclks 10mhz bit rate. sixteen time slots are defined and allocated as follows: table 3-2. p2 multiplexing sequence mxdo (from base board) mxdi (from mvme760) time slot signal name time slot signal name 0rts3 0cts3 1dtr3 1dsr3/mid1 2 llb3/modsel 2 dcd3 3 rlb3 3 tm3/mid0 4rts4 4 ri3 5dtr4 5cts4 6 llb4 6 dsr4/mid3 7 rlb4 7 dcd4 8idreq * 8 tm4/mid2 9 reserved 9 ri4 10 reserved 10 lanpwr 11 reserved 11 reserved 12 reserved 12 reserved 13 reserved 13 reserved 14 reserved 14 reserved 15 reserved 15 genio_present * .com .com .com .com .com 4 .com u datasheet
functional description 3-19 3 abort switch (s1) the abort switch is located on the led mezzanine. when activated by software, the abort switch can generate an interrupt signal from the base board to the processor at a user-programmable level. the interrupt is normally used to abort program execution and return control to the ppcbug debugger firmware located in the MVME1603/1604 eprom and flash memory. the interrupt signal reaches the processor module via isa bus interrupt line irq8 * . the signal is also available at pin pb7 of the z8536 cio device, which handles various status signals, serial i/o lines, and counters. the interrupter connected to the abort switch is an edge-sensitive circuit, filtered to remove switch bounce. .com .com .com .com .com 4 .com u datasheet
block diagram 3-20 3 reset switch (s2) the reset switch is located on the led mezzanine. the reset switch resets all onboard devices; it also drives a sysreset * signal if the MVME1603/1604 is the system controller. the reset switch may be disabled by software. the vmechip2 includes both a global and a local reset driver. when the vmechip2 operates as the vmebus system controller, the reset driver provides a global system reset by asserting the vmebus signal sysreset * . a sysreset * signal may be generated by the reset switch, a power-up reset, a watchdog timeout, or by a control bit in the lcsr in the vmechip2. sysreset * remains asserted for at least 200 ms, as required by the vmebus specification. similarly, the vmechip2 provides an input signal and a control bit to initiate a local reset operation. by setting a control bit, software can maintain a board in a reset state, disabling a faulty board from participating in normal system operation. the local reset driver is enabled even when the vmechip2 is not the system controller. a local reset may be generated by the reset switch, a power-up reset, a watchdog timeout, a vmebus sysreset * signal, or a control bit in the gcsr. note for an MVME1603/1604 without the vmebus option (i.e., with no vmechip2), the lcsr control bit is not available to reset the module. in this case, the watchdog timer is allowed to time out to reset the MVME1603/1604. .com .com .com .com .com 4 .com u datasheet
functional description 3-21 3 front panel indicators (ds1 - ds6) there are six leds on the MVME1603/1604 front panel: chs , bfl , cpu , pci , fus , and sys . o chs (ds1, yellow). checkstop; driven by the mpc603/604 status lines on the MVME1603/1604. lights when a halt condition from the processor is detected. o bfl (ds2, yellow). board failure; lights when the brdfail * signal line is active. o cpu (ds3, green). cpu activity; lights when the dbb * (data bus busy) signal line on the processor bus is active. o pci (ds4, green). pci activity; lights when the irdy * (initiator ready) signal line on the pci bus is active. this indicates that the pci mezzanine (if installed) is active. o fus (ds5, green). fuse ok; lights when +5vdc, +12vdc, and C 12vdc power is available from the base board to the transition module and remote devices. note the circuitry monitored by the fus led differs between the mvme1600-001 and mvme1600-011 versions of the base board. the differences are detailed under the respective base board descriptions in chapter 1. because the fus led monitors the status of several voltages on the mvme1600-001, it does not directly indicate the condition of any single fuse. if the led flickers or goes out, check all the fuses (polyswitches). o sys (ds6, green). system controller; lights when the vmechip2 in the MVME1603/1604 is the vmebus system controller. .com .com .com .com .com 4 .com u datasheet
block diagram 3-22 3 polyswitches (resettable fuses) the mvme1600-001 and mvme1600-011 base boards draw fused +5vdc, +12vdc, and C12vdc power from the vmebus backplane through connectors p1 and p2. the 3.3vdc power (used by the isa super i/o device on the base board, and by the pm603 or pm604 processor/memory mezzanine) is derived on-board from the +5vdc. the following table lists the fuses with the voltages they protect on the respective base boards. mvme1600-001 base board the mvme1600-001 base board furnishes +12vdc, C12vdc, and +5vdc power to the mvme760 transition module through polyswitches (resettable fuses) f4, f2, and f3. the mvme760 uses these voltage sources to power the serial port drivers and any lan transceivers connected to the transition module. the fus led (ds5) on the mvme1600-001 front panel illuminates when all three voltages are available. the fused +5vdc power is also supplied to the base boards keyboard and mouse connectors and to the 14-pin combined led-mezzanine/remote- reset connector, j1. in addition, the mvme1600-001 base board provides +5vdc to the scsi bus termpwr signal through fuse f1, located near the front panel scsi connector. the fus led (ds5) on the front panel monitors the scsi bus termpwr signal along with the other operating voltages; when the mvme1600-001 is connected to an scsi bus, either directly or via the mvme760 module, scsi terminator power helps illuminate the fus led. table 3-3. fuse assignments by base board fuse mvme1600-001 mvme1600-011 f1 +5vdc (scsi) +5vdc f2 C12vdc +12vdc f3 +5vdc f4 +12vdc .com .com .com .com .com 4 .com u datasheet
functional description 3-23 3 note because any device on the scsi bus can provide termpwr , and because the fus led monitors the status of several voltages, the led does not directly indicate the condition of any single fuse. if the led flickers or goes out, check all the fuses (polyswitches). mvme1600-011 base board the mvme1600-011 base board provides +5vdc power to the remote led/switch connector (j4) through a 1a fuse (f1) located between p1 and p2. (j4 provides a separate connection point for a remote control and indicator panel, making it unnecessary to share the led mezzanine connector for that purpose.) if none of the leds light and the abort and reset switches do not operate, check fuse f1. the mvme1600-011 base board provides +12vdc power to the ethernet transceiver interface through a 1a fuse (f2) located between p1 and p2. the fus led lights to indicate that +12vdc is available. with the mvme712m transition module connected, the yellow ds1 led on the mvme712m also signals the availability of lan power, indicating in turn that the fuse is good. if the ethernet transceiver fails to operate, check fuse f2. the mvme1600-011 base board supplies scsi terminator power through a 1a fuse (f1) located on the p2 adapter board. if the fuse is blown, the scsi device(s) may function erratically or not at all. with the p2 adapter board cabled to an mvme712m and with an scsi bus connected to the mvme712m, the green ds2 led on the mvme712m illuminates when scsi terminator power is available. if the ds2 led flickers during scsi bus operation, check fuse f1 on the p2 adapter board. .com .com .com .com .com 4 .com u datasheet
block diagram 3-24 3 speaker control the mvme1600-001 base board supplies a speaker_out signal to the 14-pin combined led-mezzanine/remote-reset connector, j1. when j1 is used as a remote reset connector with the led mezzanine removed, the speaker_out signal can be cabled to an external speaker to obtain a beep tone. for the pin assignments of j1, refer to table 1-2. like the mvme1600-001 base board, the mvme1600-011 supplies a speaker_out signal to the 14-pin led mezzanine connector, j1. unlike the mvme1600-001 base board, the mvme1600-011 also applies the speaker_out signal to its dedicated remote status and control connector, j4. the led mezzanine need not be removed to cable the speaker_out signal to an external speaker. for the pin assignments of j4, refer to table 1-3. pm603/604 processor/memory mezzanine module the pm603 or pm604 is the processor/memory mezzanine module that (together with an led mezzanine, an optional ram104 dram module, and an optional pci mezzanine card) plugs into the mvme1600-001 or mvme1600-011 base board to make a complete single-board computer. see figure 1-10. you have the choice of a powerpc603 ? module (the pm603) or a powerpc604 ? module (the pm604) with from 8mb to 64mb of dram, or up to 128mb of dram with a ram104. 256kb of l2 cache is available as an option. there is no parity or ecc protection on the dram. the powerpc603 is a 64-bit processor with 16kb or 32kb on-chip cache (8kb/16kb data cache and 8kb/16kb instruction cache). the powerpc604 is a 64-bit processor with 32 kb on-chip cache (16kb data cache and 16kb instruction cache). the mpc105 bridge/memory controller located on the processor/memory mezzanine provides the bridge between the powerpc microprocessor bus and the pci local bus. the memory is kept on the processor bus to get the optimum performance from the designs. electrically, the processor/memory module is a pci connection. .com .com .com .com .com 4 .com u datasheet
functional description 3-25 3 mpc604 boards have double-wide front panels to accommodate a heat sink on the powerpc604 that protrudes into the adjacent vme slot. the pm603/pm604 module accommodates additional memory. ram104 modules of 8, 16, 32, or 64mb dram are available for memory expansion. a 192mb memory module is available for the pm604 module as a factory- installed option. the processor module has sockets for 1mb of flash memory. the onboard monitor/debugger, ppcbug, resides in the flash chips. ppcbug provides: o a boot loader and extensive onboard diagnostics o a single-line assembler/disassembler o the capability to save and restore a configuration through nvram o a remote boot capability under normal operation, the flash devices are in read-only mode, their contents are pre-defined, and they are protected against inadvertent writes due to loss of power conditions. however, for programming purposes, programming voltage is always supplied to the devices and the flash contents may be modified by executing the proper program command sequence. refer to the third-party data sheet for further device-specific information and/or to the pflash ppcbug command. .com .com .com .com .com 4 .com u datasheet
block diagram 3-26 3 flash device speed is 150 ns. for this speed, software must not program romfal (first access length) and romnal (last access length) in the mpc105 device with values lower than the following minimum values for various processor external clock frequencies (hardware does not support the burst for which nal is used): ram104 memory module the ram104 is the optional dram memory mezzanine module that (together with a pm603 or pm604 processor/memory mezzanine, an led mezzanine, and an optional pci mezzanine card) plugs into the base board to make a complete MVME1603 or mvme1604 single-board computer. see figure 1-11. ram104 modules of 8, 16, 32, or 64mb are available for memory expansion. there is no parity or ecc protection on the dram. the addition of the memory module on the processor/memory module makes a stack three boards high. an MVME1603 sbc maintains a single vme slot width with this stacking, although it does brush the inter-card buffer zone. mvme1604 sbcs have a heatsink on the powerpc604 that extends well into the adjacent vme slot, so mvme604 boards have double-wide front panels. table 3-4. minimum romfal and romnal values processor external bus speed romfal minimum va lue romnal minimum va lue 8-bit access times (number of clocks) 64-bit single/burst access times (number of clocks) 25 mhz 1 1 4 32/32-32-32-32 33 mhz 2 2 5 40/40-40-40-40 40 mhz 3 3 6 48/48-48-48-48 50 mhz 5 5 8 64/64-64-64-64 66 mhz 7 7 10 80/80-80-80-80 .com .com .com .com .com 4 .com u datasheet
functional description 3-27 3 mvme760 transition module the mvme760 transition module (figure 1-4) is used in conjunction with the mvme1600-001 base board. the features of the mvme760 include: o a parallel printer port o an ethernet interface supporting both aui and 10baset connections o two eia-232-d asynchronous serial ports (identified as com1 and com2 on the front panel) o two synchronous serial ports (ports 3 and 4) serial interface modules the synchronous serial ports on the mvme760 are configurable via serial interface modules (sims), used in conjunction with the appropriate jumper settings. the sims are small plug-in printed circuit boards which contain all the circuitry needed to convert a ttl-level port to the standard voltage levels needed by various industry-standard serial interfaces, such as eia- 232, eia-530, etc. the following types of sims are available: for additional information about serial interface modules, refer to the mvme760 users manual (part number vme760a/um) and to the sim705 installation guide (part number sim705a/ih). table 3-5. module type identification model number module type part number sim705-001 eia-232 dce 01-w3876b xx sim705-002 eia-232 dte 01-w3877b xx sim705-003 eia-530 dce 01-w3878b xx sim705-004 eia-530 dte 01-w3879b xx .com .com .com .com .com 4 .com u datasheet
block diagram 3-28 3 mvme712m transition module the mvme712m transition module (figure 1-6) and p2 adapter board are used in conjunction with the mvme1600-011 base board. the features of the mvme712m include: o a parallel printer port (through the p2 adapter) o an ethernet interface supporting aui connections (through the p2 adapter) o four eia-232-d multiprotocol serial ports (through the p2 adapter) o an scsi interface (through the p2 adapter) for connection to both internal and external devices o socket-mounted scsi terminating resistors for end-of-cable or middle-of-cable configurations o provision for modem connection o green led for scsi terminator power; yellow led for ethernet transceiver power the features of the p2 adapter board include: o a 50-pin connector for scsi cabling to the mvme712m and/or to other scsi devices o socket-mounted scsi terminating resistors for end-of-cable or middle-of-cable configurations o fused scsi teminator power developed from the +5vdc present at connector p2 o a 64-pin din connector to interface the eia-232-d, parallel, scsi, and ethernet signals to the mvme712m .com .com .com .com .com 4 .com u datasheet
4 4-1 4 connector pin assignments this chapter summarizes the pin assignments for the following groups of interconnect signals for the MVME1603/mvme1604: o connectors with pin assignments common to both the mvme1600- 001 and mvme1600-011 base boards o connectors with pin assignments specific to the mvme1600-001 base board connector table led mezzanine connector 4-1 mpu mezzanine connector 4-2 cpu connector 4-3 dram mezzanine connectors 4-4, 4-5 pci mezzanine connector 4-6 vmebus connector p1 4-7 ethernet 10baset connector 4-8 disk drive connector 4-9 connector table vmebus p2 connector 4-10 scsi connector 4-11 graphics connector 4-12 keyboard and mouse connectors 4-13, 4-14 ethernet aui connector (mvme760) 4-15 parallel i/o connector(mvme760) 4-16 serial ports 1 and 2 (mvme760) 4-17 serial ports 3 and 4 (mvme760) 4-18 .com .com .com .com .com 4 .com u datasheet
common connectors 4-2 4 o connectors with pin assignments specific to the mvme1600-011 base board the following tables furnish pin assignments only. for detailed descriptions of the various interconnect signals, consult the support information documentation package for the MVME1603/ mvme1604 sbc or the support information sections of the mvme760 or mvme712m transition module documentation as necessary. common connectors the following tables describe connectors used with the same pin assignments by both the mvme1600-001 and the mvme1600-011 base boards. connector table vmebus p2 connector 4-19 scsi connector (at mvme712m) 4-20 ethernet aui connector 4-21 parallel i/o connector 4-22 serial ports 1-4 (at mvme712m) 4-23 serial ports 3 and 4 (at front panel) 4-24 .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-3 4 led mezzanine connector a 16-pin connector (j1 on the base board) supplies the interface between the base board and the led mezzanine module. on the base board, this connector is a 2x7 header. on the led mezzanine, it is a 2x7 surface- mount socket strip. the pin assignments are as follows: mpu mezzanine connector a 152-pin connector (j14 on the mvme1600-001 base board, j17 on the mvme1600-011) supplies the interface between the base board and the mpu mezzanine module. the pin assignments are listed in the following table. table 4-1. led mezzanine connector 1 gnd resetsw * 2 3 irq_5 abortsw * 4 5 pciled * failled * 6 7 lanled * statled * 8 9 fuseled * runled * 10 11 sbsyled * sconled * 12 13 +5v spkr 14 .com .com .com .com .com 4 .com u datasheet
common connectors 4-4 4 table 4-2. mpu mezzanine connector 1 pciclk1 pciclk2 2 3 pciclk3 pciclk4 4 5 gnd gnd 6 7ckstop * cpuled * 8 9 ibcint * abort * 10 11 lanint * vme2pciint * 12 13 scsiint * grint * 14 15 pmcirq * kbirq 16 17 mouseirq com1irq 18 19 com2irq gnd parptirq 20 21 cio_irq * scc_irq * 22 23 flpyirq * irq _ b * 24 25 smi * sreset * 26 27 nmi lbreset * 28 29 tben pureset * 30 31 tck tdo1 32 33 tdi1 tms 34 35 pmcp * trst * 36 37 pmcreq * pmcgnt * 38 39 isa_mstr * flshreq * 40 41 sd7 flshack * 42 43 sd6 reserved 44 45 sd5 ramcfg * 46 47 sd4 cpucnfg * 48 49 sd3 x_ior * 50 51 sd2 x_iow * 52 53 sd1 sa1 54 55 sd0 sa0 56 57 C12v +5v +12v 58 59 serr * perr * 60 61 sdone lock * 62 63 sbo * devsel * 64 65 gnd gnd 66 67 irdy * trdy * 68 69 frame * stop * 70 71 gnd gnd 72 73 pcignt * ack64 * 74 75 pcireq * req64 * 76 .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-5 4 77 reserved par 78 79 cbe0 * cbe1 * 80 81 cbe2 * cbe3 * 82 83 ad0 ad1 84 85 ad2 ad3 86 87 ad4 ad5 88 89 ad6 ad7 90 91 ad8 ad9 92 93 ad10 ad11 94 95 ad12 gnd ad13 96 97 ad14 ad15 98 99 ad16 ad17 100 101 ad18 ad19 102 103 ad20 ad21 104 105 ad22 ad23 106 107 ad24 ad25 108 109 ad26 ad27 110 111 ad28 ad29 112 113 ad30 ad31 114 115 pci_resv5 par64 116 117 cbe4 * cbe5 * 118 119 cbe6 * cbe7 * 120 121 ad32 ad33 122 123 ad34 ad35 124 125 ad36 ad37 126 127 ad38 ad39 128 129 ad40 ad41 130 131 ad42 ad43 132 133 ad44 +3.3v ad45 134 135 ad46 ad47 136 137 ad48 ad49 138 139 ad50 ad51 140 141 ad52 ad53 142 143 ad54 ad55 144 145 ad56 ad57 146 147 ad58 ad59 148 149 ad60 ad61 150 151 ad62 ad63 152 table 4-2. mpu mezzanine connector (continued) .com .com .com .com .com 4 .com u datasheet
common connectors 4-6 4 cpu connector a 190-pin connector (j2 on the pm603/pm604 processor/memory mezzanine module) provides access to the processor bus (mpu bus) and some mpc105 bridge/memory controller signals. it can be used to add l2 cache memory (refer to the pm603/pm604 users manual ) or to upgrade the processor. the pin assignments are listed in the following table. .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-7 4 table 4-3. cpu connector 1pa0 pa1 2 3pa2 pa3 4 5pa4 pa5 6 7pa6 pa7 8 9pa8 pa9 10 11 pa10 pa11 12 13 pa12 pa13 14 15 pa14 pa15 16 17 pa16 pa17 18 19 pa18 gnd pa19 20 21 pa20 pa21 22 23 pa22 pa23 24 25 pa24 pa25 26 27 pa26 pa27 28 29 pa28 pa29 30 31 pa30 pa31 32 33 pa_par0 pa_par1 34 35 pa_par2 pa_par3 36 37 ape * rsrv * 38 39 pd0 pd1 40 41 pd2 pd3 42 43 pd4 pd5 44 45 pd6 pd7 46 47 pd8 pd9 48 49 pd10 pd11 50 51 pd12 pd13 52 53 pd14 pd15 54 55 pd16 pd17 56 57 pd18 +5v pd19 58 59 pa20 pd21 60 61 pd22 pd23 62 63 pd24 pd25 64 65 pd26 pd27 66 67 pd28 pd29 68 69 pd30 pd31 70 71 pd32 pd33 72 73 pd34 pd35 74 75 pd36 pd37 76 .com .com .com .com .com 4 .com u datasheet
common connectors 4-8 4 77 pd38 pd39 78 79 pd40 pd41 80 81 pd42 pd43 82 83 pd44 pd45 84 85 pd46 pd47 86 87 pd48 pd49 88 89 pa50 pd51 90 91 pd52 pd53 92 93 pd54 pd55 94 95 pd56 gnd pd57 96 97 pd58 pd59 98 99 pd60 pd61 100 101 pd62 pd63 102 103 pdpar0 pdpar1 104 105 pdpar2 pdpar3 106 107 pdpar4 pdpar5 108 109 pdpar6 pdpar7 110 111 no connection no connection 112 113 dpe * dbdis * 114 115 tt0 tsiz0 116 117 tt1 tsiz1 118 119 tt2 tsiz2 120 121 tt3 tc0 122 123 tt4 tc1 124 125 ci * tc2 126 127 wt * cse0 128 129 global * cse1 130 131 shared * dbwo * 132 133 aack * +3.3v ts * 134 135 arty * xats * 136 137 drty * tbst * 138 139 ta * no connection 140 141 tea * no connection 142 143 no connection dbg * 144 145 no connection dbb * 146 147 no connection abb * 148 149 tclk_out cpugnt * 150 151 l2prsnt0 * cpureq * 152 table 4-3. cpu connector (continued) .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-9 4 153 l2adsc * ibcint * 154 155 l2baa * mchk * 156 157 l2dirtyi * smi * 158 159 l2dirtyo * ckstpi * 160 161 l2doe * ckstpo * 162 163 l2dwe1 * halted (n/c) 164 165 l2hit * tlbisync * 166 167 l2tale tben 168 169 l2taloe * suspend * 170 171 l2toe * gnd drvmod0 172 173 l2twe * drvmod1 (n/c 174 175 l2tv naprun (n/c 176 177 l2prsnt1 * qreq * 178 179 sreset * qack * 180 181 hreset * cputdo 182 183 gnd cputdi 184 185 cpuclk1 cputck 186 187 cpuclk2 cputms 188 189 cpuclk3 cputrst * 190 table 4-3. cpu connector (continued) .com .com .com .com .com 4 .com u datasheet
common connectors 4-10 4 dram expansion connectors two 100-pin connectors (j3 and j4 on the pm603/pm604 processor/memory mezzanine module) supply the interface between the processor/memory mezzanine and the ram104 dram mezzanine. the pin assignments are listed in the following two tables. table 4-4. dram mezzanineconnector 1 1 gnd ma_bb0 2 51 gnd bcasb7 * 52 3 ma_bb1 ma_bb2 4 53 bmd0 gnd 54 5 ma_bb3 gnd 6 55 gnd bmd1 56 7 gnd ma_bb4 8 57 bmd2 gnd 58 9 ma_bb5 ma_bb6 10 59 gnd bmd3 60 11 ma_bb7 gnd 12 61 bmd4 gnd 62 13 gnd ma_bb8 14 63 gnd bmd5 64 15 ma_bb9 ma_bb10 16 65 bmd6 +5v 66 17 ma_bb11 gnd 18 67 +5v bmd7 68 19 gnd bweb2 * 20 69 bmd8 gnd 70 21 brasb0 * gnd 22 71 gnd bmd9 72 23 gnd brasb1 * 24 73 bmd10 +5v 74 25 brasb2 * gnd 26 75 +5v bmd11 76 27 gnd brasb3 * 28 77 bmd12 gnd 78 29 brasb4 * gnd 30 79 gnd bmd13 80 31 gnd brasb5 * 32 81 bmd14 +5v 82 33 brasb6 * gnd 34 83 +5v bmd15 84 35 gnd brasb7 * 36 85 bmd16 gnd 86 37 bcasb0 * gnd 38 87 gnd bmd17 88 39 gnd bcasb1 * 40 89 bmd18 +5v 90 41 bcasb2 * gnd 42 91 +5v bmd19 92 43 gnd bcasb3 * 44 93 bmd20 gnd 94 45 bcasb4 * gnd 46 95 gnd bmd21 96 47 gnd bcasb5 * 48 97 bmd22 +5v 98 49 bcasb6 * gnd 50 99 +5v bmd23 100 .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-11 4 pci mezzanine card connectors two 64-pin connectors (j11 and j12 on the base board) supply the interface between the base board and an optional pci mezzanine card (pmc). the pin assignments are listed in the following table. vmebus connector p1 two 96-pin connectors (p1 and p2) supply the interface between the base board and the vmebus. p1 provides power and vme signals for 24-bit addressing and 16-bit data. its pin assignments are set by the vmebus specification. they are listed in table 4-7. table 4-5. dram mezzanineconnector 2 1bweb3 * gnd 2 51 gnd bmd48 52 3 gnd bmd24 4 53 bmd49 gnd 54 5 bmd25 gnd 6 55 gnd bmd50 56 7 gnd bmd26 8 57 bmd51 +3.3v 58 9 bmd27 gnd 10 59 +3.3v bmd52 60 11 gnd bmd28 12 61 bmd53 gnd 62 13 bmd29 gnd 14 63 gnd bmd54 64 15 gnd bmd30 16 65 bmd55 +3.3v 66 17 bmd31 gnd 18 67 +3.3v bmd56 68 19 gnd bmd32 20 69 bmd57 gnd 70 21 bmd33 gnd 22 71 gnd bmd58 72 23 gnd bmd34 24 73 bmd59 +3.3v 74 25 bmd35 gnd 26 75 +3.3v bmd60 76 27 gnd bmd36 28 77 bmd61 gnd 78 29 bmd37 gnd 30 79 gnd bmd62 80 31 gnd bmd38 32 81 bmd63 +3.3v 82 33 bmd39 gnd 34 83 +3.3v bdp0 84 35 gnd bmd40 36 85 bdp1 bdp2 86 37 bmd41 gnd 38 87 bdp3 gnd 88 39 gnd bmd42 40 89 gnd bdp4 90 41 bmd43 gnd 42 91 bdp5 bdp6 92 43 gnd bmd44 44 93 bdp7 +3.3v 94 45 bmd45 gnd 46 95 +3.3v no conn. 96 47 gnd bmd46 48 97 b3siz0 b3siz1 98 49 bmd47 gnd 50 99 b4siz0 b4siz1 100 .com .com .com .com .com 4 .com u datasheet
common connectors 4-12 4 table 4-6. pci mezzanine card connector j11 j12 1tck C12v 2 1 +12v trst * 2 3 gnd inta * 4 3 tms tdo2 4 5intb * intc * 6 5 tdo1 gnd 6 7pncp * +5v 8 7 gnd not used 8 9intd * not used 10 9 not used not used 10 11 gnd not used 12 11 pull-up +3.3v 12 13 clk gnd 14 13 lbreset * pull-down 14 15 gnd pmcgnt * 16 15 +3.3v pull-down 16 17 pmcreq * +5v 18 17 not used gnd 18 19 +5v ad31 20 19 ad30 ad29 20 21 ad28 ad27 22 21 gnd ad26 22 23 ad25 gnd 24 23 ad24 +3.3v 24 25 gnd cbe3 * 26 25 idsel ad23 26 27 ad22 ad21 28 27 +3.3v ad20 28 29 ad19 +5v 30 29 ad18 gnd 30 31 +5v ad17 32 31 ad16 cbe2 * 32 33 frame * gnd 34 33 gnd not used 34 35 gnd irdy * 36 35 tdry * +3.3v 36 37 devsel * +5v 38 37 gnd stop * 38 39 gnd lock * 40 39 perr * gnd 40 41 sdone * sbo * 42 41 +3.3v serr * 42 43 par gnd 44 43 cbe1 * gnd 44 45 +5v ad15 46 45 ad14 ad13 46 47 ad12 ad11 48 47 gnd ad10 48 49 ad09 +5v 50 49 ad08 +3.3v 50 51 gnd cbe0 * 52 51 ad07 not used 52 53 ad06 ad05 54 53 +3.3v not used 54 55 ad04 gnd 56 55 not used gnd 56 57 +5v ad03 58 57 not used not used 58 59 ad02 ad01 60 59 gnd not used 60 61 ad00 +5v 62 61 ack64 * +3.3v 62 63 gnd req64 * 64 63 gnd not used 64 .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-13 4 table 4-7. vmebus connector p1 row a row b row c 1 vd0 vbbsy * vd8 1 2 vd1 vbclr * vd9 2 3 vd2 vacfail * vd10 3 4 vd3 vbgin0 * vd11 4 5 vd4 vbgout0 * vd12 5 6 vd5 vbgin1 * vd13 6 7 vd6 vbgout1 * vd14 7 8 vd7 vbgin2 * vd15 8 9 gnd vbgout2 * gnd 9 10 vsysclk vbgin3 * vsysfail * 10 11 gnd vbgout3 * vberr * 11 12 vds1 * vbr0 * vsysreset * 12 13 vds0 * vbr1 * vlword 13 14 vwrite * vbr2 * va m 5 1 4 15 gnd vbr3 * va 2 3 1 5 16 vdtack * va m 0 va 2 2 1 6 1 7 g n d va m 1 va 2 1 1 7 18 vas * va m 2 va 2 0 1 8 1 9 g n d va m 3 va 1 9 1 9 20 viack * gnd va18 20 21 viackin * vserclk va17 21 22 viackout * vserdat va16 22 2 3 va m 4 g n d va 1 5 2 3 24 va7 virq7 * va 1 4 2 4 25 va6 virq6 * va 1 3 2 5 26 va5 virq5 * va 1 2 2 6 27 va4 virq4 * va 1 1 2 7 28 va3 virq3 * va 1 0 2 8 29 va2 virq2 * va 9 2 9 30 va1 virq1 * va 8 3 0 31 C12v +5vstdby +12v 31 32 +5v +5v +5v 32 .com .com .com .com .com 4 .com u datasheet
common connectors 4-14 4 ethernet 10baset connector the MVME1603/mvme1604 provides both aui and 10baset lan connections. the 10baset interface is implemented with a standard rj45 socket. for mvme1600-001 base boards, the rj45 connector is located on the mvme760 transition module; for mvme1600-011 base boards, it is located on the front panel of the board itself. the pin assignments are listed in the following table. table 4-8. ethernet 10baset connector 1entd 2entd * 3enrd 4 no connection 5 no connection 6enrd * 7 no connection 8 no connection .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-15 4 disk drive connector a 34-pin connector (j6 on the base board) supplies the interface between the base board and an optional disk drive. the disk drive may take the form of a mezzanine board or a separate module. the pin assignments are listed in the following table. table 4-9. disk drive mezzanine connector 1 gnd f_densel 2 3 gnd no connection 4 5 gnd f_msen0 6 7 no connection f_index * 8 9 gnd f_mtr0 * 10 11 gnd f_dr1 * 12 13 no connection f_dr0 * 14 15 gnd f_mtr1 * 16 17 f_msen1 f_dir * 18 19 gnd f_step * 20 21 gnd f_wdata * 22 23 gnd f_wgate * 24 25 gnd f_trk0 * 26 27 gnd f_wp * 28 29 gnd f_rdata * 30 31 gnd f_hdsel * 32 33 gnd f_dskchg * 34 .com .com .com .com .com 4 .com u datasheet
mvme1600-001 connectors 4-16 4 mvme1600-001 connectors the following tables summarize the pin assignments of connectors that are specific to MVME1603/mvme1604 modules based on the mvme1600- 001 base board, used with mvme760 transition modules. vmebus connector p2 two 96-pin connectors (p1 and p2) supply the interface between the base board and the vmebus. p1 provides power and vme signals for 24-bit addressing and 16-bit data. its pin assignments are set by the vmebus specification. p2 rows a and c provide power and interface signals to the mvme760 transition module. p2 row c supplies the base board with power, with the upper eight vmebus address lines, and with an additional 16 vmebus data lines. the pin assignments for p2 are listed in the following table. scsi connector the scsi connector for the mvme1600-001 base board is a 68-pin high- density connector located on the front panel. the pin assignments for the scsi connector are listed in table 4-19. .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-17 4 table 4-10. scsi connector 1 gnd scsid12 * 35 2 gnd scsid13 * 36 3 gnd scsid14 * 37 4 gnd scsid15 * 38 5 gnd scscdp 1 39 6 gnd scsid0 * 40 7 gnd scsid 1* 41 8 gnd scsid2 * 42 9 gnd scsid3 * 43 10 gnd scsid4 * 44 11 gnd scsid5 * 45 12 gnd scsid6 * 46 13 gnd scsid7 * 47 14 gnd scscdp0 48 15 gnd gnd 49 16 gnd gnd 50 17 scsi_tp scsi_tp 51 18 scsi_tp scsi_tp 52 19 no connection no connection 53 20 gnd gnd 54 21 gnd satn * 55 22 gnd gnd 56 23 gnd sbsy * 57 24 gnd sack * 58 25 gnd srst * 59 26 gnd smsg * 60 27 gnd ssel * 61 28 gnd sc_d * 62 29 gnd sreq * 63 30 gnd si_o * 64 31 gnd scsid8 * 65 32 gnd scsid9 * 66 33 gnd scsid10 * 67 34 gnd scsid11 * 68 .com .com .com .com .com 4 .com u datasheet
mvme1600-001 connectors 4-18 4 graphics connector the mvme1600-001 base board has a db15 graphics connector located on the front panel. the pin assignments for the graphics connector are listed in the following table. table 4-11. graphics connector 1 gired 2 gigreen 3 giblue 4 gip2 5 gnd 6 gnd 7 gnd 8 gnd 9 no connection 10 gnd 11 gip0 12 gip1 13 gihsync 14 givsync 15 gip3 .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-19 4 keyboard and mouse connectors the mvme1600-001 base board has two 6-pin circular din connectors for the keyboard and mouse located on the front panel. the pin assignments for those connectors are listed in the following two tables. table 4-12. keyboard connector 1k_data 2 no connection 3 gnd 4 +5vkbm 5k_clk 6 no connection table 4-13. mouse connector 1m_data 2 no connection 3 gnd 4 +5vkbm 5m_clk 6 no connection .com .com .com .com .com 4 .com u datasheet
mvme1600-001 connectors 4-20 4 ethernet aui connector the MVME1603/mvme1604 provides both aui and 10baset lan connections. for the mvme1600-001 base board, the aui interface is implemented with a db15 (j11) connector located on the mvme760 transition module. the pin assignments are listed in the following table. table 4-14. ethernet aui connector (mvme760) 1 gnd 2c+ 3t+ 4 gnd 5r+ 6 gnd 7 no connection 8 gnd 9c- 10 t- 11 gnd 12 r- 13 +12v 14 gnd 15 no connection .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-21 4 parallel i/o connector both versions of the base board provide parallel i/o connections. for the mvme1600-001 base board, the parallel interface is implemented with an ieee p1284 36-pin connector (j10) located on the mvme760 transition module. the pin assignments are listed in the following table. table 4-15. parallel i/o connector (mvme760) 1 prbsy gnd 19 2 prsel gnd 20 3 prack * gnd 21 4 prfault * gnd 22 5 prpe gnd 23 6 prd0 gnd 24 7 prd1 gnd 25 8 prd2 gnd 26 9 prd3 gnd 27 10 prd4 gnd 28 11 prd5 gnd 29 12 prd6 gnd 30 13 prd7 gnd 31 14 inprime * gnd 32 15 prstb * gnd 33 16 selin * gnd 34 17 autofd * gnd 35 18 pull-up no connection 36 .com .com .com .com .com 4 .com u datasheet
mvme1600-001 connectors 4-22 4 serial ports 1 and 2 the MVME1603/mvme1604 provides both asynchronous (ports 1 and 2) and synchronous/asynchronous (ports 3 and 4) serial connections. for the mvme1600-001 base board, the asynchronous interface is implemented with a pair of db9 connectors ( com1 and com2 ) located on the mvme760 transition module. the pin assignments are listed in the following table. table 4-16. serial connectionsports 1 and 2 (mvme760) 1sp n dcd 2sp n rd 3sp n td 4sp n dtr 5 gnd 6sp n dsr 7sp n rts 8sp n cts 9sp n ri .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-23 4 serial ports 3 and 4 for the mvme1600-001 base board, the synchronous/ asynchronous interface for ports 3 and 4 is implemented with a pair of 26-pin 3m-type ribbon connectors (j7 and j2) located on the board surface of the mvme760 transition module. in addition, serial port 3 has an hd26 front panel connector (j5). the pin assignments for serial ports 3 and 4 are listed in the following table. table 4-17. serial connectionsports 3 and 4 (mvme760) panel connector ribbon connector 1 no connection 1 2txd n 3 3rxd n 5 4rts n 7 5cts n 9 6 dsr n 11 7 gnd 13 8dcd n 15 9sp n _p9 17 10 sp n _p10 19 11 sp n _p11 21 12 sp n _p12 23 13 sp n _p13 25 14 sp n _p14 2 15 txci n 4 16 sp n _p16 6 17 rxci n 8 18 llb n 10 19 sp n _p19 12 20 dtr n 14 21 rlb n 16 22 ri n 18 23 sp n _p23 20 24 txco n 22 25 tm n 24 26 no connection 26 .com .com .com .com .com 4 .com u datasheet
mvme1600-011 connectors 4-24 4 mvme1600-011 connectors the following tables summarize the pin assignments of connectors that are specific to MVME1603/mvme1604 modules based on the mvme1600- 011 base board, used with mvme712m transition modules. vmebus connector p2 two 96-pin connectors (p1 and p2) supply the interface between the base board and the vmebus. p1 provides power and vme signals for 24-bit addressing and 16-bit data. its pin assignments are set by the vmebus specification. p2 rows a and c provide power and interface signals to the mvme712m transition module. p2 row c supplies the base board with power, with the upper eight vmebus address lines, and with an additional 16 vmebus data lines. the pin assignments for p2 are listed in the following table. scsi connector the scsi connector for the mvme1600-011 base board is a 50-pin connector located on the front panel of the mvme712m transition module. the pin assignments for the scsi connector are listed in table 4- 19. .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-25 4 table 4-18. vmebus connector p2 row a row b row c 1 scsid0 +5v enc * 1 2 scsid1 gnd enc 2 3 scsid2 retry * ent * 3 4 scsid3 va24 ent 4 5 scsid4 va25 enr * 5 6 scsid5 va26 enr 6 7 scsid6 va27 +12vlan 7 8 scsid7 va28 pr_std 8 9 scsidpo va29 pr_data0 9 10 satn * va30 pr_data1 10 11 sbsy * va31 pr_data2 11 12 sack * gnd pr_data3 12 13 srst * +5v pr_data4 13 14 smsg * vd16 pr_data5 14 15 ssel * vd17 pr_data6 15 16 sc_d * vd18 pr_data7 16 17 sreq * vd19 pr_ack * 17 18 si_o * vd20 pr_bsy 18 19 txd3 vd21 pr_pe 19 20 rxd3 vd22 pr_slct 20 21 rts3 vd23 pr_init * 21 22 cts3 gnd pr_err * 22 23 dtr3 vd24 txd1 23 24 dcd3 vd25 rxd1 24 25 txd4 vd26 rts1 25 26 rxd4 vd27 cts1 26 27 rts4 vd28 txd2 27 28 trxc4 vd29 rxd2 28 29 cts4 vd30 rts2 29 30 dtr4 vd31 cts2 30 31 dcd4 gnd dtr2 31 32 rtxc4 +5v dcd2 32 .com .com .com .com .com 4 .com u datasheet
mvme1600-011 connectors 4-26 4 table 4-19. scsi connector (mvme712m) 1 gnd db00 * 26 2 gnd db01 * 27 3 gnd db02 * 28 4 gnd db03 * 29 5 gnd db04 * 30 6 gnd db05 * 31 7 gnd db06 * 32 8 gnd db07 * 33 9 gnd dbp * 34 10 gnd gnd 35 11 gnd gnd 36 12 gnd gnd 37 13 reserved termpwr 38 14 gnd gnd 39 15 gnd gnd 40 16 gnd atn * 41 17 gnd gnd 42 18 gnd bsy * 43 19 gnd ack * 44 20 gnd rst * 45 21 gnd msg * 46 22 gnd sel * 47 23 gnd d/c * 48 24 gnd req * 49 25 gnd o/i * 50 .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-27 4 ethernet aui connector the MVME1603/mvme1604 provides both aui and 10baset lan connections. for the mvme1600-011 base board, the aui interface is implemented with a db15 connector located on the mvme712m transition module. the pin assignments are listed in the following table. table 4-20. ethernet aui connector (mvme712m) 1 no connection 2c+ 3t+ 4 no connection 5r+ 6 gnd 7 no connection 8 no connection 9c- 10 t- 11 no connection 12 r- 13 +12v 14 no connection 15 no connection .com .com .com .com .com 4 .com u datasheet
mvme1600-011 connectors 4-28 4 parallel i/o connector both versions of the base board provide parallel i/o connections. for the mvme1600-011 base board, the parallel interface is implemented with a 36-pin centronics-type socket connector located on the mvme712m transition module. the pin assignments are listed in the following table. table 4-21. parallel i/o connector (mvme712m) 1prstb * gnd 19 2 prd0 gnd 20 3 prd1 gnd 21 4 prd2 gnd 22 5 prd3 gnd 23 6 prd4 gnd 24 7 prd5 gnd 25 8 prd6 gnd 26 9 prd7 gnd 27 10 prack * gnd 28 11 prbsy gnd 29 12 prpe gnd 30 13 prsel inprime * 31 14 no connection prfault * 32 15 no connection no connection 33 16 gnd no connection 34 17 no connection no connection 35 18 no connection no connection 36 .com .com .com .com .com 4 .com u datasheet
connector pin assignments 4-29 4 serial ports 1-4 for the mvme1600-011 base board, the interface for asynchronous ports 1 and 2 and for synchronous/asynchronous ports 3 and 4 is implemented with four eia-232-d db25 connectors (j7-j10) located on the front panel of the mvme712m transition module. in addition, ports 3 and 4 have hd26 front panel connectors (j2, j3) on the base board. the pin assignments for serial ports 1-4 on the mvme712m are listed in the following table. table 4-22. serial connectionsmvme712m ports 1-4 1 no connection 2 etxd n 3 erxd n 4erts n 5 ects n 6edsr n 7gnd 8edcd n 9 no connection 10 no connection 11 no connection 12 no connection 13 no connection 14 no connection 15 ertxc ( port 4 only ) 16 no connection 17 errxc ( port 4 only ) 18 no connection 19 no connection 20 edtr n 21 no connection 22 no connection 23 no connection 24 ettxc ( port 4 only ) 25 no connection .com .com .com .com .com 4 .com u datasheet
mvme1600-011 connectors 4-30 4 the pin assignments for serial ports 3 and 4 at the mvme1600-011 front panel are listed in the following table. for detailed descriptions of the various interconnect signals, consult the support information documentation package for the MVME1603/mvme1604 sbc or the support information sections of the mvme760 or mvme712m transition module documentation as necessary. table 4-23. serial connectionsmvme1600-011 ports 3 and 4 1 no connection 2txd n 3rxd n 4rts n 5cts n 6sp n dsr 7gnd 8dcd n 9 no connection 10 no connection 11 no connection 12 no connection 13 no connection 14 no connection 15 sp n txc 16 no connection 17 sp n rxc 18 sp n ll 19 no connection 20 dtr n 21 sp n rl 22 sp n ri 23 no connection 24 sp n txco 25 sp n tm 26 no connection .com .com .com .com .com 4 .com u datasheet
5 5-1 5 ppcbug overview the powerpc debugger, ppcbug, is a powerful evaluation and debugging tool for systems built around motorola powerpc microcomputers. facilities are available for loading and executing user programs under complete operator control for system evaluation. the powerpc debugger provides a high degree of functionality and user friendliness, and yet stresses portability and ease of maintenance. it achieves good portability and comprehensibility because it was written entirely in the c programming language, except where necessary to use assembler functions. ppcbug includes commands for display and modification of memory, breakpoint and tracing capabilities, a powerful assembler and disassembler useful for patching programs, and a self-test at power-up feature which verifies the integrity of the system. various ppcbug routines that handle i/o, data conversion, and string functions are available to user programs through the system call handler. ppcbug consists of three parts: o a command-driven user-interactive software debugger. it is hereafter referred to as the debugger or ppcbug. o a set of command-driven diagnostics, which is hereafter referred to as the diagnostics. o a user interface which accepts commands from the system console terminal. when using ppcbug, you will operate out of either the debugger directory or the diagnostic directory. the debugger prompt ( ppc1-bug or ppc1-diag ) tells you the current directory. .com .com .com .com .com 4 .com u datasheet
overview 5-2 5 because ppcbug is command-driven, it performs its various operations in response to user commands entered at the keyboard. the flow of control in ppcbug is described in the ppcbug firmware package users manual . when you enter a command, ppcbug executes the command and the prompt reappears. however, if you enter a command that causes execution of user target code (e.g., go ), then control may or may not return to ppcbug, depending on the outcome of the user program. the ppcbug is similar to previous motorola firmware debugging packages (e.g., mvme147bug, mvme167bug, mvme187bug), with differences due to microprocessor architectures. these are primarily reflected in the instruction mnemonics, register displays, addressing modes of the assembler/disassembler, and the passing of arguments to the system calls. memory requirements ppcbug requires a total of 512kb of read/write memory (i.e., dram). the debugger allocates this space from the top of memory. for example, a system containing 64mb ($04000000) of read/write memory will place the ppcbug memory page at locations $03f80000 to $03ffffff. ppcbug implementation ppcbug is written largely in the c programming language, providing benefits of portability and maintainability. where necessary, assembly language has been used in the form of separately compiled program modules containing only assembler code. no mixed-language modules are used. physically, ppcbug is contained in two socketed 32-pin plcc/clcc flash devices that together provide 1mb of storage. the executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a precalculated checksum contained in the flash devices), is tested for an expected zero. .com .com .com .com .com 4 .com u datasheet
ppcbug 5-3 5 using the debugger ppcbug is command-driven; it performs its various operations in response to commands that you enter at the keyboard. when the ppc1-bug prompt appears on the screen, the debugger is ready to accept debugger commands. when the ppc1-diag prompt appears on the screen, the debugger is ready to accept diagnotics commands. to switch from one mode to the other, enter sd . what you key in is stored in an internal buffer. execution begins only after you press the return or enter key. this allows you to correct entry errors, if necessary, with the control characters described in the ppcbug firmware package users manual , chapter 1. after the debugger executes the command, the prompt reappears. however, if the command causes execution of user target code (for example go ) then control may or may not return to the debugger, depending on what the user program does. for example, if a breakpoint has been specified, then control returns to the debugger when the breakpoint is encountered during execution of the user program. alternately, the user program could return to the debugger by means of the system call handler routine return (described in the ppcbug firmware package users manual , chapter 5). for more about this, refer to the gd , go , and gt command descriptions in the ppcbug firmware package users manual , chapter 3. a debugger command is made up of the following parts: o the command name, either uppercase or lowercase (e.g., md or md ). o any required arguments, as specified by command. o at least one space before the first argument. precede all other arguments with either a space or comma. o one or more options. precede an option or a string of options with a semicolon ( ; ). if no option is entered, the commands default option conditions are used. .com .com .com .com .com 4 .com u datasheet
using the debugger 5-4 5 debugger commands the individual debugger commands are listed in the following table. the commands are described in detail in the ppcbug firmware package users manual , chapter 2 . note you can list all the available debugger commands by entering the help ( he ) command alone. you can view the syntax for a particular command by entering he and the command mnemonic, as listed below. table 5-1. debugger commands command description as one line assembler bc block of memory compare bf block of memory fill bi block of memory initialize bm block of memory move br breakpoint insert nobr breakpoint delete bs block of memory search bv block of memory verify cm concurrent mode nocm no concurrent mode cnfg configure board information block cs checksum dc data conversion dma block of memory move ds one line disassembler du dump s-records echo echo string env set environment gd go direct (ignore breakpoints) gevboot global environment variable boot gevdel global environment variable delete .com .com .com .com .com 4 .com u datasheet
ppcbug 5-5 5 gevdump global environment variable(s) dump gevedit global environment variable edit gevinit global environment variable initialization gevshow global environment variable(s) display gn go to next instruction go go execute user program gt go to temporary breakpoint he help ioc i/o control for disk ioi i/o inquiry iop i/o physical (direct disk access) iot i/o teach for configuring disk controller lo load s-records from host ma macro define/display noma macro delete mae macro edit mal enable macro listing nomal disable macro listing mar load macros maw save macros md, mds memory display menu system menu mm memory modify mmd memory map diagnostic ms memory set mw memory write nab automatic network boot nbh network boot operating system, halt nbo network boot operating system nioc network i/o control niop network i/o physical niot network i/o teach (configuration) nping network ping table 5-1. debugger commands (continued) command description .com .com .com .com .com 4 .com u datasheet
using the debugger 5-6 5 of offset registers display/modify pa printer attach nopa printer detach pboot bootstrap operating system pf port format nopf port detach pflash program flash memory ps put rtc into power save mode rb romboot enable norb romboot disable rd register display remote remote reset cold/warm reset rl read loop rm register modify rs register set sd switch directories set set time and date sym symbol table attach nosym symbol table detach syms symbol table display/search t trace ta terminal attach time display time and date tm transparent mode tt trace to temporary breakpoint ve verify s-records against memory ver revision/version display wl write loop table 5-1. debugger commands (continued) command description .com .com .com .com .com 4 .com u datasheet
ppcbug 5-7 5 ! caution although a command to allow the erasing and reprogramming of flash memory is available to you, keep in mind that reprogramming any portion of flash memory will erase everything currently contained in flash, including the ppc1bug debugger. diagnostic tests the individual diagnostic test sets are listed in the following table. the diagnostics are described in the ppc1bug diagnostics manual . notes you may enter command names in either uppercase or lowercase. some diagnostics depend on restart defaults that are set up only in a particular restart mode. refer to the documentation on a particular diagnostic for the correct mode. table 5-2. diagnostic test groups test set description applicability dec21040 decchip 21040 ethernet controller tests all MVME1603/1604 i82378 i82378 pci/isa bridge tests all MVME1603/1604 kbd87303 pc87303 keyboard/mouse tests not applicable to versions with -011 base board l2cache level 2 cache tests MVME1603/1604 with l2 cache only ncr ncr 53c825/53c810 scsi-2 i/o processor tests all MVME1603/1604 par87303 pc87303/87323 parallel port test all MVME1603/1604 pc16550 pc16550 uart tests all MVME1603/1604 pcibus generic pci/pmc slot test all MVME1603/1604 ram local ram tests all MVME1603/1604 rtc mk48t18 real-time clock tests all MVME1603/1604 scc z85230 serial communication controller tests all MVME1603/1604 vga544x video diagnostics tests not applicable to versions with -011 base board vme2 vmechip2 vme interface asic tests all MVME1603/1604 z8536 z8536 counter/timer tests all MVME1603/1604 .com .com .com .com .com 4 .com u datasheet
using the debugger 5-8 5 .com .com .com .com .com 4 .com u datasheet
6 6-1 6 cnfg and env commands overview you can use the factory-installed debug monitor, ppcbug, to modify certain parameters contained in the powerpc board's non-volatile ram (nvram), also known as battery backed-up ram (bbram). o the board information block in nvram contains various elements concerning operating parameters of the hardware. use the ppcbug command cnfg to change those parameters. o use the ppcbug command env to change configurable ppcbug parameters in nvram. the cnfg and env commands are both described in the ppcbug firmware package user's manual (part number ppcbuga1/um). refer to that manual for general information about their use and capabilities. the following paragraphs present additional information about cnfg and env that is specific to the ppcbug debugger, along with the parameters that can be configured with the env command. .com .com .com .com .com 4 .com u datasheet
cnfg - configure board information block 6-2 6 cnfg - configure board information block use this command to display and configure the board information block, which is resident within the nvram. the board information block contains various elements detailing specific operational parameters of the powerpc board. the board structure for the powerpc board is as shown in the following example for an MVME1603-001: the parameters that are quoted are left-justified character (ascii) strings padded with space characters, and the quotes () are displayed to indicate the size of the string. parameters that are not quoted are considered data strings, and data strings are right-justified. the data strings are padded with zeroes if the length is not met. the board information block is factory-configured before shipment. there is no need to modify block parameters unless the nvram is corrupted. refer to the programmers reference guide (part number v1600-1a/pg) for the actual location and other information about the board information block. refer to the ppcbug firmware package user's manual (part number ppcbuga1/um) for a description of cnfg and examples. board (pwa) serial number = mot001673590 board identifier = MVME1603-001 artwork (pwa) identifier = 01-w3015f01a mpu clock speed = 066 bus clock speed = 033 ethernet address = 08003e20c983 local scsi identifier = 07 system serial number = 1463725 system identifier = motorola MVME1603-00x .com .com .com .com .com 4 .com u datasheet
cnfg and env commands 6-3 6 env - set environment use the env command to view and/or configure interactively all ppcbug operational parameters that are kept in non-volatile ram (nvram). refer to the ppcbug firmware package user's manual for a description of the use of env . additional information on registers in the vmechip2 and vme2pci asics that affect these parameters is contained in your powerpc board programmers reference guide. listed and described below are the parameters that you can configure using env . the default values shown were those in effect when this publication went to print. configuring the ppcbug parameters the parameters that can be configured using env are: bug or system environment [b/s] = s? field service menu enable [y/n] = y? b bug is the mode where no system type of support is displayed. however, system-related items are still available. s system is the standard mode of operation, and is the default mode if nvram should fail. system mode is defined in the ppcbug firmware package user's manual . (default) y display the field service menu. (default) n do not display the field service menu. .com .com .com .com .com 4 .com u datasheet
env - set environment 6-4 6 remote start method switch [g/m/b/n] = b? the remote start method switch is used when the MVME1603/mvme1604 is cross-loaded from another vme-based cpu, to start execution of the cross-loaded program. probe system for supported i/o controllers [y/n] = y? auto-initialize of nvram header enable [y/n] = y? network prep-boot mode enable [y/n] = y? g use the global control and status register (gcsr, located in the vmechip2 on powerpc board series modules) to pass and start execution of the cross- loaded program. m use the multiprocessor control register (mpcr) in shared ram to pass and start execution of the cross- loaded program. b use both the gcsr and the mpcr methods to pass and start execution of the cross-loaded program. (default) n do not use any remote start method. y accesses will be made to the appropriate system buses (e.g., vmebus, local mpu bus) to determine the presence of supported controllers. (default) n accesses will not be made to the vmebus to determine the presence of supported controllers. y nvram (prep partition) header space will be initialized automatically during board initialization. (default) n nvram header space will not be initialized automatically during board initialization. y enable prep-style network booting (same boot image from a network interface as from a mass storage device). (default) n do not enable prep-style network booting. .com .com .com .com .com 4 .com u datasheet
cnfg and env commands 6-5 6 negate vmebus sysfail* always [y/n] = n? local scsi bus reset on debugger startup [y/n] = y? local scsi bus negotiations type [a/s/n] = a? local scsi data bus width [w/n] = n? nvram bootlist (gev.fw-boot-path) boot enable [y/n] = y? note when enabled, the gev (global environment variable) boot takes priority over all other boots, including autoboot and network boot. nvram bootlist (gev.fw-boot-path) boot at power-up only [y/n] = n? y negate the vmebus sysfail * signal during board initialization. n negate the vmebus sysfail * signal after successful completion or entrance into the bug command monitor. (default) y local scsi bus is reset on debugger setup. (default) n local scsi bus is not reset on debugger setup. a asynchronous scsi bus negotiation. (default) s synchronous scsi bus negotiation. n none. w wide scsi (16-bit bus). n narrow scsi (8-bit bus). (default) y give boot priority to devices defined in the fw-boot- path global environment variable (gev). (default) n do not give boot priority to devices listed in the fw- boot-path gev. y give boot priority to devices defined in the fw-boot- path gev at power-up reset only. n give power-up boot priority to devices listed in the fw-boot-path gev at any reset. (default) .com .com .com .com .com 4 .com u datasheet
env - set environment 6-6 6 nvram bootlist (gev.fw-boot-path) boot abort delay = 5? the time in seconds that a boot from the nvram boot list will delay before starting the boot. the purpose for the delay is to allow you the option of stopping the boot by use of the break key. the time value is from 0-255 seconds. (default = 5 seconds) auto boot enable [y/n] = y? auto boot at power-up only [y/n] = n? auto boot scan enable [y/n] = y? auto boot scan device type list = fdisk/cdrom/tape/hdisk? the listing of boot devices displayed if the autoboot scan option is enabled. if you modify the list, follow the format shown above (uppercase letters, using forward slash as separator). y the autoboot function is enabled. (default) n the autoboot function is disabled. y autoboot is attempted at power-up reset only. n autoboot is attempted at any reset.(default) y if autoboot is enabled, the autoboot process attempts to boot from devices specified in the scan list (e.g., fdisk/cdrom/tape/hdisk ). (default) n if autoboot is enabled, the autoboot process uses the controller lun and device lun to boot. .com .com .com .com .com 4 .com u datasheet
cnfg and env commands 6-7 6 auto boot controller lun = 00? refer to the ppcbug firmware package user's manual for a listing of disk/tape controller modules currently supported by ppcbug. (default = $00) auto boot device lun = 00? refer to the ppcbug firmware package user's manual for a listing of disk/tape devices currently supported by ppcbug. (default = $00) auto boot partition number = 00? which disk partition is to be booted, as specified in the powerpc reference platform (prp) specification. if set to zero, the firmware will search the partitions in order (1, 2, 3, 4) until it finds the first bootable partition. that is then the partition that will be booted. other acceptable values are 1, 2, 3, or 4. in these four cases, the partition specified will be booted without searching. auto boot abort delay = 7? the time in seconds that the autoboot sequence will delay before starting the boot. the purpose for the delay is to allow you the option of stopping the boot by use of the break key. the time value is from 0-255 seconds. (default = 7 seconds) auto boot default string [null for an empty string] = ? you may specify a string (filename) which is passed on to the code being booted. the maximum length of this string is 16 characters. (default = null string) rom boot enable [y/n] = n? rom boot at power-up only [y/n] = y? y the romboot function is enabled. n the romboot function is disabled. (default) y romboot is attempted at power-up only. (default) n romboot is attempted at any reset. .com .com .com .com .com 4 .com u datasheet
env - set environment 6-8 6 rom boot enable search of vmebus [y/n] = n? rom boot abort delay = 5? the time in seconds that the romboot sequence will delay before starting the boot. the purpose for the delay is to allow you the option of stopping the boot by use of the break key. the time value is from 0-255 seconds. (default = 5 seconds) rom boot direct starting address = fff00000? the first location tested when ppcbug searches for a romboot module. (default = $fff00000) rom boot direct ending address = fffffffc? the last location tested when ppcbug searches for a romboot module. (default = $fffffffc) network auto boot enable [y/n] = y? network auto boot at power-up only [y/n] = n? y vmebus address space, in addition to the usual areas of memory, will be searched for a romboot module . n vmebus address space will not be accessed by romboot. (default) y the network auto boot (netboot) function is enabled. (default) n the netboot function is disabled. y netboot is attempted at power-up reset only. n netboot is attempted at any reset. (default) .com .com .com .com .com 4 .com u datasheet
cnfg and env commands 6-9 6 network auto boot controller lun = 00? refer to the ppcbug firmware package user's manual for a listing of disk/tape controller modules currently supported by ppcbug. (default = $00) network auto boot device lun = 00? refer to the ppcbug firmware package user's manual for a listing of disk/tape controller modules currently supported by ppcbug. (default = $00) network auto boot abort delay = 5? the time in seconds that the netboot sequence will delay before starting the boot. the purpose for the delay is to allow you the option of stopping the boot by use of the break key. the time value is from 0-255 seconds. (default = 5 seconds) network auto boot configuration parameters offset (nvram) = 00001000? the address where the network interface configuration parameters are to be saved/retained in nvram; these parameters are the necessary parameters to perform an unattended network boot. a typical offset might be $1000, but this value is application-specific. (default = $00001000) ! caution if you use the niot debugger command, these parameters need to be saved somewhere in the offset range $00000000 through $00000fff. the niot parameters do not exceed 128 bytes in size. the setting of this env pointer determines their location. if you have used the same space for your own program information or commands, they will be overwritten and lost. you can relocate the network interface configuration parameters in this space by using the env command to change the network auto boot configuration parameters offset from its default of $00001000 to the value you need to be clear of your data within nvram. .com .com .com .com .com 4 .com u datasheet
env - set environment 6-10 6 memory size enable [y/n] = y? memory size starting address = 00000000? the default starting address is $00000000. memory size ending address = 02000000? the default ending address is the calculated size of local memory. if the memory start is changed from $00000000, this value will also need to be adjusted. dram speed in nano seconds = 60? the default setting for this parameter will vary depending on the speed of the dram memory parts installed on the board. the default is set to the slowest speed found on the available banks of dram memory. rom first access length (0 - 31) = 10? this is the value programmed into the mpc105 romfal field (memory control configuration register 8: bits 23-27) to indicate the number of clock cycles used in accessing the rom. the lowest allowable romfal setting is $00; the highest allowable is $1f. the value to enter depends on processor speed; refer to your processor/memory mezzanine module users manual for appropriate values. the default value varies according to the systems bus clock speed. y memory will be sized for self test diagnostics. (default) n memory will not be sized for self test diagnostics. .com .com .com .com .com 4 .com u datasheet
cnfg and env commands 6-11 6 rom next access length (0 - 15) = 0? the value programmed into the mpc105 romnal field (memory control configuration register 8: bits 28-31) to represent wait states in access time for nibble (or burst) mode rom accesses. the lowest allowable romnal setting is $0; the highest allowable is $f. the value to enter depends on processor speed; refer to your processor/memory mezzanine module users manual for appropriate values. the default value varies according to the systems bus clock speed. dram parity enable [on-detection/always/never - o/a/n] = o? l2 cache parity enable [on-detection/always/never - o/a/n] = o? pci interrupts route control registers (pirq0/1/2/3) = 0a0b0e0f? initializes the pirqx (pci interrupts) route control registers in the ibc (pci/isa bus bridge controller). the env parameter is a 32-bit value that is divided by 4 to yield the values for route control registers pirq0/1/2/3. the default is determined by system type. for details on pci/isa interrupt assignments and for suggested values to enter for this parameter, refer to the maskable interrupts section of chapter 4 in the MVME1603/ mvme1604 programmers reference guide . o dram parity is enabled upon detection. (default) a dram parity is always enabled. n dram parity is never enabled. o l2 cache parity is enabled upon detection. (default) a l2 cache parity is always enabled. n l2 cache parity is never enabled. .com .com .com .com .com 4 .com u datasheet
env - set environment 6-12 6 configuring the vmebus interface env asks the following series of questions to set up the vmebus interface for the mvme160 3 /mvme1604 series modules. to perform this configuration, you should have a working knowledge of the vme2pci and vmechip2 asics as described in the programmers reference guide . vme2pci master master enable [y/n] = y? vme2pci slave enable #1 [y/n] = y? vme2pci slave starting address #1 = 01000000? controls the starting address of the first pci memory space for the vme2pcis slave interface. pci memory accesses within the range of this starting address and its associated ending address are passed on to the vmechip2, after modification by the address offset value. only the upper 16 bits of this address are significant. (default = $01000000) vme2pci slave ending address #1 = 1fffffff? controls the ending address of the first pci memory space for the vme2pcis slave interface. only the upper 16 bits of this address are significant. (default = $1fffffff) y set up and enable the vmebus interface (default) n do not set up or enable the vmebus interface. y set up and enable vme2pci slave address decoder #1 (default) n do not set up or enable vme2pci slave address decoder #1. .com .com .com .com .com 4 .com u datasheet
cnfg and env commands 6-13 6 vme2pci slave address offset #1 = 00000000? used in translating the most significant 16 bits of the address to be presented to the vmechip2 from the pci bus. the address presented is equal to the sum of pci address (bits 31-16) and the value of this register (bits 31-16). bits 15-00 will be zero. (default = $00000000) vme2pci slave enable #2 [y/n] = y? vme2pci slave starting address #2 = 20000000? controls the starting address of the second pci memory space for the vme2pcis slave interface. pci memory accesses within the range of this starting address and its associated ending address are passed on to the vmechip2, after modification by the address offset value. only the upper 16 bits of this address are significant. (default = $20000000) vme2pci slave ending address #2 = 2fffffff? controls the ending address of the second pci memory space for the vme2pcis slave interface. only the upper 16 bits of this address are significant. (default = $2fffffff) vme2pci slave address offset #2 = d0000000? used in translating the most significant 16 bits of the address to be presented to the vmechip2 from the pci bus. the address presented is equal to the sum of pci address (bits 31-16) and the value of this register (bits 31-16). bits 15-00 will be zero. (default = $d0000000) slave address decoders the slave address decoders are used to allow another vmebus master to access a local resource of the MVME1603/1604. there are two slave address decoders set. they are set up as follows: y set up and enable vme2pci slave address decoder #2. (default) n do not set up or enable vme2pci slave address decoder #2. .com .com .com .com .com 4 .com u datasheet
env - set environment 6-14 6 slave enable #1 [y/n] = y? slave starting address #1 = 00000000? base address of the local resource that is accessible by the vmebus. (default = $0, base of local memory) slave ending address #1 = 03ffffff? ending address of the local resource that is accessible by the vmebus. (default = end of calculated memory) slave address translation address #1 = 80000000? enables the vmebus address and the local address to differ. the value in this register is the base address of the local resource associated with the starting and ending address selection from the previous questions. (default = $80000000) slave address translation select #1 = fe000000? defines which bits of the address are significant. a logical 1 indicates significant address bits, and a logical 0 is nonsignificant. (default = $fe000000) slave control #1 = 03ff? defines the access restriction for the address space defined with this slave address decoder. (default = $03ff) slave enable #2 [y/n] = n? slave starting address #2 = 00000000? y yes, set up and enable the slave address decoder #1. (default) n do not set up and enable the slave address decoder #1. y yes, set up and enable the slave address decoder #2. n do not set up and enable the slave address decoder #2. (default) .com .com .com .com .com 4 .com u datasheet
cnfg and env commands 6-15 6 base address of the local resource that is accessible by the vmebus. (default = $00000000) slave ending address #2 = 00000000? ending address of the local resource that is accessible by the vmebus. (default = $00000000) slave address translation address #2 = 00000000? enables the vmebus address and the local address to differ. the value in this register is the base address of the local resource associated with the starting and ending address selection from the previous questions. (default = $00000000) slave address translation select #2 = 00000000? defines which bits of the address are significant. a logical 1 indicates significant address bits, and a logical 0 is nonsignificant. (default = $00000000) slave control #2 = 0000? defines the access restriction for the address space defined with this slave address decoder. (default = $0000) master enable #1 [y/n] = y? y yes, set up and enable the master address decoder #1. (default) n do not set up and enable the master address decoder #1. .com .com .com .com .com 4 .com u datasheet
env - set environment 6-16 6 master starting address #1 = 00000000 the base address of the vmebus resource that is accessible from the local bus. (default = $00000000, end of calculated local memory) master ending address #1 = 1fffffff? the ending address of the vmebus resource that is accessible from the local bus. (default = $1fffffff) master control #1 = 0d? defines the access characteristics for the address space defined with this master address decoder. (default = $0d) master enable #2 [y/n] = n? master starting address #2 = 00000000? base address of the vmebus resource that is accessible from the local bus. (default = $00000000) master ending address #2 = 00000000? ending address of the vmebus resource that is accessible from the local bus. (default = $00000000) master control #2 = 00? defines the access characteristics for the address space defined with this master address decoder. (default = $00) master enable #3 [y/n] = n? y yes, set up and enable the master address decoder #2. n do not set up and enable the master address decoder #2. (default) y yes, set up and enable the master address decoder #3. n do not set up and enable the master address decoder #3. (default) .com .com .com .com .com 4 .com u datasheet
cnfg and env commands 6-17 6 master starting address #3 = 00000000? base address of the vmebus resource that is accessible from the local bus. (default = $00000000) master ending address #3 = 00000000? ending address of the vmebus resource that is accessible from the local bus. (default = $00000000) master control #3 = 00? defines the access characteristics for the address space defined with this master address decoder. (default = $00) master enable #4 [y/n] = n? master starting address #4 = 00000000? base address of the vmebus resource that is accessible from the local bus. (default = $00000000) master ending address #4 = 00000000? ending address of the vmebus resource that is accessible from the local bus. (default = $00000000) y yes, set up and enable the master address decoder #4. n do not set up and enable the master address decoder #4. (default) .com .com .com .com .com 4 .com u datasheet
env - set environment 6-18 6 master address translation address #4 = 00000000? enables the vmebus address and the local address to differ. the value in this register is the base address of the vmebus resource associated with the starting and ending address selection from the previous questions. (default = $00000000) master address translation select #4 = 00000000? defines which bits of the address are significant. a logical 1 indicates significant address bits, and a logical 0 is nonsignificant. (default = $00000000) master control #4 = 00? defines the access characteristics for the address space defined with this master address decoder. (default = $00) short i/o (vmebus a16) enable [y/n] = y? short i/o (vmebus a16) control = 01? defines the access characteristics for the address space defined with the short i/o address decoder. (default = $01) f-page (vmebus a24) enable [y/n] = y? f-page (vmebus a24) control = 02? defines the access characteristics for the address space defined with the f-page address decoder. (default = $02) vmec2 vector base #1 = 06? defines the base interrupt vector for the component specified. (default: vmechip2 vector 1 = $06) vmec2 vector base #2 = 07? y yes, enable the short i/o address decoder. (default) n do not enable the master address decoder. y yes, enable the f-page address decoder. (default) n do not enable the f-page address decoder. .com .com .com .com .com 4 .com u datasheet
cnfg and env commands 6-19 6 defines the base interrupt vector for the component specified. (default: vmechip2 vector 2 = $07) vmec2 gcsr group base address = 00? defines the group address ($ffff xx 00) in short i/o for this board. (default = $00) vmec2 gcsr board base address = 00? specifies the base address ($ffff00 x 0) in short i/o for this board. (default = $00) vmebus global time out code = 02? controls the vmebus time-out interval when the MVME1603/ 1604 is system controller. (default = $02, 256 microseconds) vmebus access time out code = 02? this controls the local-bus-to-vmebus access time-out interval. (default = $02, 32 milliseconds) .com .com .com .com .com 4 .com u datasheet
env - set environment 6-20 6 .com .com .com .com .com 4 .com u datasheet
a a-1 a related documentation motorola computer group documents this product has an installation and use manual which provides the necessary information to properly install and operate the board. this manual along with additional product documentation may be ordered by using any of the following methods: o contacting your local motorola sales office. o accessing the world wide web site http//: www.mcg.mot.com (listed on the back cover of this and other mcg manuals) and selecting product literature. o (usa and canada only) - contacting the literature center via phone or fax at the numbers listed under product literature at mcgs world wide web site (above). any supplements issued for a specific revision of a manual or guide are furnished with that document. the type and revision level of a specific manual are indicated by the last three characters of the document number, such as /ih2 (the second revision of an installation manual); a supplement bears the same number as a manual but has two additional characters that indicate the revision level of the supplement, for example /ih2a1 (the first supplement to the second edition of the installation manual). .com .com .com .com .com 4 .com u datasheet
motorola computer group documents a-2 a note motorola documents marked with a * in the above list can be purchased as a set under part number lk-v1600-1 . table a-1. motorola computer group documents document title publication number MVME1603/mvme1604 single board computer installation and use* v1600-1a/ih MVME1603/mvme1604 single board computer programmers reference guide* v1600-1a/pg pm603/pm604 processor/memory mezzanine module and ram104 dram memory module users manual* pm603a/um ppcbug firmware package users manual (parts 1 and 2)* ppcbuga1/um ppcbuga2/um ppc1bug diagnostics manual* ppc1diaa/um mvme712m transition module and p2 adapter board users manual mvme712m/d mvme760 transition module users manual vme760a/um sim705 serial interface module installation guide sim705a/ih .com .com .com .com .com 4 .com u datasheet
related documentation a-3 a manufacturers documents for additional information, refer to the following table for manufacturers data sheets or users manuals. as an additional help, a source for the listed document is also provided. please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice. to further assist your development effort, motorola has collected some of the non-motorola documents in this list from the suppliers. this bundle can be ordered as part number 68-pcikit . table a-2. manufacturers documents document title and source publication number powerpc 603 tm risc microprocessor technical summary motorola literature and printing distribution services p.o. box 20924 phoenix, arizona 85036-0924 telephone: (602) 994-6561 fax: (602) 994-6430 mpc603/d powerpc 603 tm risc microprocessor users manual motorola literature and printing distribution services p.o. box 20924 phoenix, arizona 85036-0924 telephone: (602) 994-6561 fax: (602) 994-6430 or ibm microelectronics mail stop a25/862-1 powerpc marketing 1000 river street essex junction, vermont 05452-4299 telephone: 1-800-powerpc telephone: 1-800-769-3772 fax: 1-800-powerfax fax: 1-800-769-3732 mpc603um/ad mpr603umu-01 .com .com .com .com .com 4 .com u datasheet
manufacturers documents a-4 a powerpc 604 tm risc microprocesso r users manual motorola literature and printing distribution services p.o. box 20924 phoenix, arizona 85036-0924 telephone: (602) 994-6561 fax: (602) 994-6430 or ibm microelectronics mail stop a25/862-1 powerpc marketing 1000 river street essex junction, vermont 05452-4299 telephone: 1-800-powerpc telephone: 1-800-769-3772 fax: 1-800-powerfax fax: 1-800-769-3732 mpc604um/ad mpr604umu-01 mpc105 pci bridge/memory controller users manual motorola literature and printing distribution services p.o. box 20924 phoenix, arizona 85036-0924 telephone: (602) 994-6561 fax: (602) 994-6430 mpc105um/ad powerpc tm microprocessor family: the programming environments motorola literature and printing distribution services p.o. box 20924 phoenix, arizona 85036-0924 telephone: (602) 994-6561 fax: (602) 994-6430 or ibm microelectronics mail stop a25/862-1 powerpc marketing 1000 river street essex junction, vermont 05452-4299 telephone: 1-800-powerpc telephone: 1-800-769-3772 fax: 1-800-powerfax fax: 1-800-769-3732 mpcfpe/ad mprppcfpe-01 table a-2. manufacturers documents (continued) document title and source publication number .com .com .com .com .com 4 .com u datasheet
related documentation a-5 a alpine tm vga family - cl-gd544x technical reference manual fourth edition cirrus logic, inc. (or nearest sales office) 3100 west warren avenue fremont, california 94538-6423 telephone: (510) 623-8300 fax: (510) 226-2180 385439-004 decchip 21040 ethernet lan controller for pci hardware reference manual digital equipment corporation maynard, massachusetts decchip information line telephone (united states and canada): 1-800-332-2717 tty (united states only): 1-800-332-2515 telephone (outside north america): +1-508-568-6868 ec-n0752-72 pc87303vul ( super i/o tm sidewinder lite) floppy disk controller, keyboard controller, real-time clock, dual uarts, ieee 1284 parallel port, and ide interface national semiconductor corporation customer support center (or nearest sales office) 2900 semiconductor drive p.o. box 58090 santa clara, california 95052-8090 telephone: 1-800-272-9959 pc87303vul pc87323vf ( super i/o tm sidewinder) floppy disk controller, keyboard controller, real-time clock, dual uarts, ieee 1284 parallel port, and ide interface national semiconductor corporation customer support center (or nearest sales office) 2900 semiconductor drive p.o. box 58090 santa clara, california 95052-8090 telephone: 1-800-272-9959 pc87323vf table a-2. manufacturers documents (continued) document title and source publication number .com .com .com .com .com 4 .com u datasheet
manufacturers documents a-6 a m48t18 cmos 8k x 8 timekeeper tm sram data sheet sgs-thomson microelectronics group marketing headquarters (or nearest sales office) 1000 east bell road phoenix, arizona 85022 telephone: (602) 867-6100 m48t18 ds1643 nonvolatile timekeeping ram data manual dallas semiconductor 4401 south beltwood parkway dallas, texas 75244-3292 ds1643/ ds1643lpm 82378 system i/o (sio) pci-to-isa bridge controller intel corporation literature sales p.o. box 7641 mt. prospect, illinois 60056-7641 telephone: 1-800-548-4725 290473-003 sym 53cxx (was ncr 53c8xx) family pci-scsi i/o processors programming guide symbios logic inc. 1731 technology drive, suite 600 san jose, ca95110 telephone: (408) 441-1080 hotline: 1-800-334-5454 j10931i scc (serial communications controller) users manual (for z85230 and other zilog parts) zilog, inc. 210 east hacienda ave., mail stop c1-0 campbell, california 95008-6600 telephone: (408) 370-8016 fax: (408) 370-8056 dc-8293-02 table a-2. manufacturers documents (continued) document title and source publication number .com .com .com .com .com 4 .com u datasheet
related documentation a-7 a z8536 cio counter/timer and parallel i/o unit product specification and users manual (in z8000 ? family of products data book) zilog, inc. 210 east hacienda ave., mail stop c1-0 campbell, california 95008-6600 telephone: (408) 370-8016 fax: (408) 370-8056 dc-8319-00 cs4231 parallel interface, multimedia audio codec data sheet crystal semiconductor corporation 4210 south industrial drive p.o. box 17847 austin, texas 78744-7847 telephone: 1-800-888-5016 telephone: (512) 445-7222 fax: (512) 445-7581 ds111pp4 csb4231/4248 evaluation board data sheet crystal semiconductor corporation 4210 south industrial drive p.o. box 17847 austin, texas 78744-7847 telephone: 1-800-888-5016 telephone: (512) 445-7222 fax: (512) 445-7581 ds111db4 award classic kb42 keyboard controller firmware for the national semiconductor pc87323vul-iab superi/o tm device award software international, inc. sales and marketing 777 e. middlefield road mountain view, california 94043 telephone: (415) 968-4433 award classic kb42 table a-2. manufacturers documents (continued) document title and source publication number .com .com .com .com .com 4 .com u datasheet
related specifications a-8 a related specifications for additional information, refer to the following table for related specifications. as an additional help, a source for the listed document is also provided. please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice. table a-3. related specifications document title and source publication number ansi small computer system interface-2 (scsi-2), draft document global engineering documents 15 inverness way east englewood, co 80112-5704 telephone: 1-800-854-7179 telephone: (303) 792-2181 x3.131.1990 ansi std x3t9.2, 1994 at attachment interface for disk drives global engineering documents 15 inverness way east englewood, co 80112-5704 telephone: 1-800-854-7179 telephone: (303) 792-2181 ansi x3.221 bidirectional parallel port interface specification institute of electrical and electronics engineers, inc. publication and sales department 345 east 47th street new york, new york 10017-21633 telephone: 1-800-678-4333 ieee standard 1284 ieee - common mezzanine card specification (cmc) institute of electrical and electronics engineers, inc. publication and sales department 345 east 47th street new york, new york 10017-21633 telephone: 1-800-678-4333 p1386 draft 2.0 .com .com .com .com .com 4 .com u datasheet
related documentation a-9 a ieee - pci mezzanine card specification (pmc) institute of electrical and electronics engineers, inc. publication and sales department 345 east 47th street new york, new york 10017-21633 telephone: 1-800-678-4333 p1386.1 draft 2.0 ieee standard for local area networks: carrier sense multiple access with collision detection (csma/cd) access method and physical layer specifications institute of electrical and electronics engineers, inc. publication and sales department 345 east 47th street new york, new york 10017-21633 telephone: 1-800-678-4333 ieee 802.3 information technology - local and metropolitan networks - part 3: carrier sense multiple access with collision detection (csma/cd) access method and physical layer specifications global engineering documents 15 inverness way east englewood, co 80112-5704 telephone: 1-800-854-7179 telephone: (303) 792-2181 (this document can also be obtained through the national standards body of member countries.) iso/iec 8802-3 interface between data terminal equipment and data circuit-terminating equipment employing serial binary data interchange (eia-232-d) electronic industries association engineering department 2001 eye street, n.w. washington, d.c. 20006 ansi/eia-232-d standard table a-3. related specifications (continued) document title and source publication number .com .com .com .com .com 4 .com u datasheet
related specifications a-10 a peripheral component interconnect (pci) local bus specification, revision 2.0 pci special interest group p.o. box 14070 portland, oregon 97214-4070 marketing/help line telephone: (503) 696-6111 document/specification ordering telephone: 1-800-433-5177or (503) 797-4207 fax: (503) 234-6762 pci local bus specification powerpc reference platform (prp) specification, third edition, version 1.0, volumes i and ii international business machines corporation power personal systems architecture 11400 burnet rd. austin, tx 78758-3493 document/specification ordering telephone: 1-800-powerpc telephone: 1-800-769-3772 telephone: 708-296-9332 mpr-ppc-rpu-02 vme64 specification vita (vmebus international trade association) 7825 e. gelding drive, suite 104 scottsdale, arizona 85260-3415 telephone: (602) 951-8866 fax: (602) 951-0720 note: an earlier version of this specification is available as: versatile backplane bus: vmebus institute of electrical and electronics engineers, inc. publication and sales department 345 east 47th street new york, new york 10017-21633 telephone: 1-800-678-4333 or microprocessor system bus for 1 to 4 byte data bureau central de la commission electrotechnique internationale 3, rue de varemb geneva, switzerland ansi/vita 1-1994 ansi/ieee standard 1014-1987 iec 821 bus table a-3. related specifications (continued) document title and source publication number .com .com .com .com .com 4 .com u datasheet
b b-1 b specifications specifications table b-1 lists the general specifications for the mvme1600-001 and mvme1600-011 base boards. the subsequent sections detail cooling requirements and fcc compliance. a complete functional description of the mvme1600-001 and mvme1600-011 base boards appears in chapter 2. specifications for the mezzanine modules (processor/memory, dram, and optional pci mezzanine) can be found in the documentation for those modules. table b-1. mvme1600-001/mvme1600-011 specifications characteristics specifications power requirements (excluding processor/ memory mezzanine, transition module, keyboard, mouse) +5vdc ( 5%), 2a typical, 3a maximum +12vdc ( 5%), 100ma maximum C12vdc ( 5%), 100ma maximum (in mvme1600-011; no C12vdc in mvme1600-001) operating temperature 0c to 55c entry air with forced-air cooling (refer to cooling requirements section) storage temperature C40c to +85 c relative humidity 5% to 90% (non-condensing) physical dimensions base board only height depth base board with front panel and connectors height depth front panel width with pm603 module with pm604 module double-high vmeboard 9.2 in. (233 mm) 6.3 in. (160 mm) 10.3 in. (262 mm) 7.4 in. (188 mm) 0.8 in. (20mm) 1.6 in. (40mm) .com .com .com .com .com 4 .com u datasheet
cooling requirements b-2 b cooling requirements the motorola MVME1603/1604 family of single board computers is specified, designed, and tested to operate reliably with an incoming air temperature range from 0 to 55 c (32 to 131 f) with forced air cooling of the entire assembly (base board and modules) at a velocity typically achievable by using a 100 cfm axial fan. temperature qualification is performed in a standard motorola vmesystem chassis. twenty-five-watt load boards are inserted in two card slots, one on each side, adjacent to the board under test, to simulate a high power density system configuration. an assembly of three axial fans, rated at 100 cfm per fan, is placed directly under the vme card cage. the incoming air temperature is measured between the fan assembly and the card cage, where the incoming airstream first encounters the module under test. test software is executed as the module is subjected to ambient temperature variations. case temperatures of critical, high power density integrated circuits are monitored to ensure component vendors specifications are not exceeded. while the exact amount of airflow required for cooling depends on the ambient air temperature and the type, number, and location of boards and other heat sources, adequate cooling can usually be achieved with 10 cfm and 490 lfm flowing over the module. less airflow is required to cool the module in environments having lower maximum ambients. under more favorable thermal conditions, it may be possible to operate the module reliably at higher than 55 c with increased airflow. it is important to note that there are several factors, in addition to the rated cfm of the air mover, which determine the actual volume and speed of air flowing over a module. .com .com .com .com .com 4 .com u datasheet
specifications b-3 b emc compliance the MVME1603/mvme1604 single board computer was tested in an emc-compliant chassis and meets the requirements for en55022 class b equipment. compliance was achieved under the following conditions: o shielded cables on all external i/o ports. o cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel. o conductive chassis rails connected to earth ground. this provides the path for connecting shields to earth ground. o front panel screws properly tightened. for minimum rf emissions, it is essential that the conditions above be implemented. failure to do so could compromise the emc compliance of the equipment containing the module. .com .com .com .com .com 4 .com u datasheet
emc compliance b-4 b .com .com .com .com .com 4 .com u datasheet
c c-1 c serial interconnections introduction as described in previous chapters of this manual, the MVME1603/mvme1604 serial communications interface has four ports. two of them are combined synchronous/asynchronous ports; the other two are asynchronous only. between the mvme1600-001 and mvme1600- 011 base boards, some differences exist in the implementation of the four ports. the differences are summarized in the following table. asynchronous serial ports the MVME1603/mvme1604 uses a pc87303 isasio chip from national semiconductor to implement the two asynchronous serial ports (in addition to the disk drive controller, parallel i/o, and keyboard/mouse interface). table c-1. mvme1600-001/mvme1600-011 serial ports base board serial interface mvme1600-001 2 asynchronous ports (eia-232-d dte) via p2 and mvme760 transition module 2 synchronous/asynchronous ports (eia-232-d or eia- 530 dce/dte) via p2 and mvme760 transition module mvme1600-011 2 asynchronous ports (eia-232-d dce/dte) via p2 and mvme712m transition module 2 synchronous/asynchronous ports (eia-232-d dce/dte) via p2 and mvme712m or via front panel. front panel i/o (dte only) gives full sync/async functionality on both ports; mvme712m i/o makes port 3 async only . .com .com .com .com .com 4 .com u datasheet
introduction c-2 c the asynchronous ports provided by the isasio device are routed through p2 and the associated transition module. the ttl-level signals from the isasio chip are buffered through ttl drivers and series resistors. the eia-232-d drivers and receivers that complete the asynchronous serial interface are located on the mvme760 (for the mvme1600-001 base board) or mvme712m (for the mvme1600-011 base board) transition module. the MVME1603/mvme1604 hardware supports asynchronous serial baud rates of 110b/s to 38.4kb/s. for detailed programming information, refer to the pci and isa bus discussions in the MVME1603/mvme1604 single board computer programmer's reference guide and to the vendor documentation for the isasio device. synchronous serial ports the MVME1603/mvme1604 uses a zilog z85230 escc (enhanced serial communications controller) with a 10mhz clock to implement the two synchronous/asynchronous serial communications ports, which for the mvme1600-001 base board are routed through p2 and for the mvme1600-011 base board are routed through the front panel as well as p2. the z85230 handles both synchronous (sdlc/hdlc) and asynchronous protocols. the hardware supports asynchronous serial baud rates of 110b/s to 38.4kb/s and synchronous baud rates of up to 2.5mb/s. each port supports the cts, dcd, rts, and dtr control signals, as well as the txd and rxd transmit/receive data signals and txc/rxc synchronous clock signals. since not all modem control lines are available in the z85230, a z8536 cio device is used to provide the missing modem lines. in addition to complementing the z85230 escc by supplying modem control lines not present on the z85230 escc, the z8536 cio device provides a way to request the module id of the synchronous/asynchronous serial ports on the transition module. refer to the z8536 data sheet and to the MVME1603/mvme1604 single board computer programmer's reference guide for further information. .com .com .com .com .com 4 .com u datasheet
serial interconnections c-3 c eia-232-d connections the eia-232-d standard defines the electrical and mechanical aspects of this serial interface. the interface employs unbalanced (single-ended) signaling and is generally used with db25 connectors, although other connector styles (e.g., db9 and rj45) are sometimes used as well. table c-2 lists the standard eia-232-d interconnections. not all pins listed in the table are necessary in every application. to interpret the information correctly, remember that the eia-232-d serial interface was developed to connect a terminal to a modem. serial data leaves the sending device on a transmit data (txd) line and arrives at the receiving device on a receive data (rxd) line. when computing equipment is interconnected without modems, one of the units must be configured as a terminal (data terminal equipment: dte) and the other as a modem (data circuit-terminating equipment: dce). since computers are normally configured to work with terminals, they are said to be configured as a modem in most cases. table c-2. eia-232-d interconnect signals pin number signal mnemonic signal name and description 1 not used. 2txd transmit data . data to be transmitted; input to modem from terminal. 3 rxd receive data . data which is demodulated from the receive line; output from modem to terminal. 4rts request to send . input to modem from terminal when required to transmit a message. with rts off, the modem carrier remains off. when rts is turned on, the modem immediately turns on the carrier. 5cts clear to send . output from modem to terminal to indicate that message transmission can begin. when a modem is used, cts follows the off-to-on transition of rts after a time delay. 6 dsr data set ready . output from modem to terminal to indicate that the modem is ready to send or receive data. 7sg signal ground . common return line for all signals at the modem interface. 8dcd data carrier detect . output from modem to terminal to indicate that a valid carrier is being received. 9-14 not used. .com .com .com .com .com 4 .com u datasheet
eia-232-d connections c-4 c notes 1. a high eia-232-d signal level is +3 to +15 volts. a low level is - 3 to - 15 volts. connecting units in parallel may produce out- of-range voltages and is contrary to specifications. 2. the eia-232-d interface is intended to connect a terminal to a modem. when computers are connected without modems, one computer must be configured as a modem and the other as a terminal. interface characteristics the eia-232-d interface standard specifies all parameters for serial binary data interchange between dte and dce devices using unbalanced lines. eia-232-d transmitter and receiver parameters applicable to the MVME1603/mvme1604 are listed in the following tables. 15 txc transmit clock (dce). output from modem to terminal; clocks data from the terminal to the modem. 16 not used. 17 rxc receive clock . output from terminal to modem; clocks input data from the terminal to the modem. 18, 19 not used. 20 dtr data terminal ready . input to modem from terminal; indicates that the terminal is ready to send or receive data. 21 not used. 22 ri ring indicator . output from modem to terminal; indicates that an incoming call is present. the terminal causes the modem to answer the phone by carrying dtr true while ri is active.. 23 not used. 24 txc transmit clock (dte). input to modem from terminal; same function as txc on pin 15. 25 bsy busy . input to modem from terminal; a positive eia signal applied to this pin causes the modem to go off-hook and make the associated phone busy. table c-2. eia-232-d interconnect signals (continued) pin number signal mnemonic signal name and description .com .com .com .com .com 4 .com u datasheet
serial interconnections c-5 c the MVME1603/mvme1604 conforms to eia-232-d specifications. note that although the eia-232-d standard recommends the use of short interconnection cables not more than 50 feet (15m) in length, longer cables are permissible provided the total load capacitance measured at the interface point and including signal terminator does not exceed 2500pf. eia-530 connections the eia-530 interface complements the eia-232-d interface in function. the eia-530 standard defines the mechanical aspects of this interface, which is used for transmission of serial binary data, both synchronous and table c-3. eia-232-d interface transmitter characteristics parameter value unit minimum maximum output voltage (with load resistance of 3000 w to 7000 w ) 8.5 v open circuit output voltage 12 v short circuit output current (to ground or any other interconnection cable conductor) 100 ma power-off output resistance 300 w output transition time (for a transition region of - 3v to +3v and with total load capacitance, includ- ing connection cable, of less than 2500pf) 2 m s open circuit slew rate 30 v/ m s table c-4. eia-232-d interface receiver characteristics parameter va lue unit minimum maximum input signal voltage 25 v input high threshold voltage 2.25 v input low threshold voltage 0.75 v input hysteresis 1.0 v input impedance ( - 15v < v in < +15v) 3000 7000 w .com .com .com .com .com 4 .com u datasheet
eia-530 connections c-6 c asynchronous. it is adaptable to balanced (double-ended) as well as unbalanced (single-ended) signaling and offers the possibility of higher data rates than eia-232-d with the same db25 connector. table c-2 lists the eia-530 interconnections that are available at mvme760 serial ports 3 and 4 (j7 and j2 on the board surface, with port 4 also available as serial 4 on the front panel) when those ports are configured via serial interface modules as eia-530 dce or dte ports. table c-5. mvme760 eia-530 interconnect signals pin number signal mnemonic signal name and description 1 not used. 2txd_a transmit data (a). data to be transmitted; output from dte to dce. 3 rxd_a receive data (a). data which is demodulated from the receive line; input from dce to dte. 4rts_a request to send (a). output from dte to dce when required to transmit a message. 5cts_a clear to send (a). input to dte from dce to indicate that message transmission can begin. 6 dsr_a data set ready (a). input to dte from dce to indicate that the dce is ready to send or receive data. in dce configuration, always true. 7sg signal ground. common return line for all signals. 8dcd_a data carrier detect (a) . receive line signal detector output from dce to dte to indicate that valid data is being transferred to the dte on the rxd line. 9 rxc_b receive signal element timing - dce (b). control signal that clocks input data. 10 dcd_b data carrier detect (b). receive line signal detector output from dce to dte to indicate that valid data is being transferred to the dte on the rxd line. 11 txco_b transmit signal element timing - dte (b). control signal that clocks output data. 12 txc_b transmit signal element timing - dce (b). control signal that clocks input data. 13 cts_b clear to send (b). input to dte from dce to indicate that message transmission can begin. 14 txd_b transmit data (b). data to be transmitted; output from dte to dce. 15 txc_a transmit signal element timing - dce (a). control signal that clocks input data. 16 rxd_b receive data (b). data which is demodulated from the receive line; input from dce to dte. 17 rxc_a receive signal element timing - dce (a). control signal that clocks input data. 18 rts_b request to send (b). output from dte to dce when required to transmit a message. 19 ll_a local loopback (a). reroutes signal within local dce. in dte configuration, always tied inactive and driven false. in dce configuration, ignored .com .com .com .com .com 4 .com u datasheet
serial interconnections c-7 c 20 dtr_a data terminal ready (a). output from dte to dce indicating that the dte is ready to send or receive data. 21 rl_a remote loopback (a). reroutes signal within remote dce. in dte configuration, always tied inactive and driven false. in dce configuration, ignored. 22 dsr_b data set ready (b). input to dte from dce to indicate that the dce is ready to send or receive data. in dce configuration, always true. 23 dtr_b data terminal ready (b). output from dte to dce indicating that the dte is ready to send or receive data. 24 txco_a transmit signal element timing - dte (a). control signal that clocks output data. 25 tm_a test mode (a). indicates whether the local dce is under test. in dte configuration, ignored. in dce configuration, always tied inactive and driven false. table c-5. mvme760 eia-530 interconnect signals (continued) pin number signal mnemonic signal name and description .com .com .com .com .com 4 .com u datasheet
eia-530 connections c-8 c interface characteristics in specifying parameters for serial binary data interchange between dte and dce devices, the eia-530 standard assumes the use of balanced lines, except for the remote loopback, local loopback, and test mode lines, which are single-ended. balanced-line data interchange is generally employed in preference to unbalanced-line data interchange where any of the following conditions prevail: o the interconnection cable is too long for effective unbalanced operation. o the interconnection cable is exposed to extraneous noise sources that may cause an unwanted voltage in excess of 1v measured differentially between the signal conductor and circuit ground at the load end of the cable, with a 50 w resistor substituted for the transmitter. o it is necessary to minimize interference with other signals. o inversion of signals may be required (e.g., plus polarity mark to minus polarity mark may be achieved by inverting the cable pair). eia-530 interface transmitter and receiver parameters applicable to the MVME1603/mvme1604 are listed in the following tables. table c-6. eia-530 interface transmitter characteristics parameter value unit minimum maximum differential output voltage (absolute, with 100 w load) 2.0 v open circuit differential voltage output (absolute) 6.0 v output offset voltage (with 100 w load) 2.0 v short circuit output current (for any voltage between - 7v and +7v) 180 ma power off output current (for any voltage between - 7v and +7v) 100 m a output transition time (with 100 w , 15pf load) 15 ns .com .com .com .com .com 4 .com u datasheet
serial interconnections c-9 c proper grounding an important subject to consider is the use of ground pins. there are two pins labeled gnd. pin 7 is the signal ground and must be connected to the distant device to complete the circuit. pin 1 is the chassis ground , but it must be used with care. the chassis is connected to the power ground through the green wire in the power cord and must be connected to be in compliance with the electrical code. the problem is that when units are connected to different electrical outlets, there may be several volts of difference in ground potential. if pin 1 of each device is interconnected with the others via cable, several amperes of current could result. this condition may not only be dangerous for the small wires in a typical cable, but may also produce electrical noise that causes errors in data transmission. that is why table c-2 and table c-5 show no connection for pin 1. normally, pin 7 ( signal ground ) should only be connected to the chassis ground at one point; if several terminals are used with one computer, the logical place for that point is at the computer. the terminals should not have a connection between the logic ground return and the chassis. table c-7. eia-530 interface receiver characteristics parameter va lue unit minimum maximum differential input voltage 12 v input offset voltage 12 v differential input high threshold voltage 200 mv differential input low threshold voltage - 200 v input hysteresis 1.0 v input impedance ( - 15v < v in < +15v) 3000 7000 w .com .com .com .com .com 4 .com u datasheet
proper grounding c-10 c .com .com .com .com .com 4 .com u datasheet
d d-1 d troubleshooting cpu boards: solving startup problems introduction in the event of difficulty with your cpu board, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. some of the procedures will return the board to the factory debugger environment. note that the board was tested under these conditions before it left the factory. the selftests may not run in all user-customized environments. table d-1. basic troubleshooting steps for all cpu boards condition possible problem try this: i. nothing works, no display on the terminal. a. if the fus (or run , pwr , +12v , or cpu led, as appli-cable) is not lit, the board may not be getting correct power. 1. make sure the system is plugged in. 2. check that the board is securely installed in its backplane or chassis. 3. check that all necessary cables are connected to the board, per this manual. 4. check for compliance with system considerations, per this manual. 5. review the installation and startup procedures, per this manual. they include a step-by-step powerup routine. try it. b. if the leds are lit, the board may be in the wrong slot. 1. for vmemodules, the cpu board should be in the first (leftmost) slot. 2. also check that the system controller function on the board is enabled, per this manual. c. the system console terminal may be configured incorrectly. configure the system console terminal per this manual. .com .com .com .com .com 4 .com u datasheet
d-2 troubleshooting cpu boards: solving startup problems d ii. there is a display on the terminal, but input from the keyboard and/or mouse has no effect. a. the keyboard or mouse may be connected incorrectly. recheck the keyboard and/or mouse connections and power. b. board jumpers may be configured incorrectly. check the board jumpers per this manual. c. you may have invoked flow control by pressing a hold or pause key, or by typing : - s press the hold or pause key again. if this does not free up the keyboard, type in: - q you are finished (done) with this troubleshooting procedure. proceed with the troubleshooting procedure for your particular cpu board, as given in the following table. table d-1. basic troubleshooting steps for all cpu boards (continued) condition possible problem try this: .com .com .com .com .com 4 .com u datasheet
introduction d-3 d table d-2. troubleshooting MVME1603/mvme1604 boards condition possible problem try this: iii. debug prompt ppc1-bug> does not appear at powerup, and the board does not autoboot. a. debugger eprom/flash may be missing 1. disconnect all power from your system. 2. check that the proper debugger eprom or debugger flash memory is installed per this manual. 3. reconnect power. 4. restart the system by double-button reset: press the reset and abort switches at the same time; release reset first, wait seven seconds, then release abort . 5. if the debug prompt appears, go to step iv or step v, as indicated. if the debug prompt does not appear, go to step vi. b. the board may need to be reset. iv. debug prompt ppc1-bug> appears at powerup, but the board does not autoboot. a. the initial debugger environment parameters may be set incorrectly. 1. start the onboard calendar clock and timer. type: set mmddyyhhmm where the characters indicate the month, day, year, hour, and minute. the date and time will be displayed. performing the next step will change some parameters that may affect your system operation. 2. type in: env;d this sets up the default parameters for the debugger environment. 3. when prompted to update non-volatile ram, type in: y 4. when prompted to reset local system, type in: y 5. after clock speed is displayed, immediately (within five seconds) press the return key: or break to exit to the system menu. then enter a 3 for go to system debugger and return: 3 now the prompt should be: ppc1-diag> (continues>) b. there may be some fault in the board hardware. ! caution .com .com .com .com .com 4 .com u datasheet
d-4 troubleshooting cpu boards: solving startup problems d 6. you may need to use the cnfg command (see your board debugger manual) to change clock speed and/or ethernet address, and then later return to: env and step 3. 7. run the selftests by typing in: st the tests take as much as 10 minutes, depending on ram size. they are complete when the prompt returns. (the onboard selftest is a valuable tool in isolating defects.) 8. the system may indicate that it has passed all the selftests. or, it may indicate a test that failed. if neither happens, enter: de any errors should now be displayed. if there are any errors, go to step vi. if there are no errors, go to step v. v. the debugger is in system mode and the board autoboots, or the board has passed selftests. a. no problems troubleshooting is done. no further troubleshooting steps are required. note even if the board passes all tests, it may still be bad. the selftest does not try out all functions in the board (for example, scsi or vmebus tests). vi. the board has failed one or more of the tests listed above, and cannot be corrected using the steps given. a. there may be some fault in the board hardware or the on-board debugging and diagnostic firmware. 1. document the problem and return the board for service. 2. phone 1-800-222-5640. you are finished (done) with this troubleshooting procedure. table d-2. troubleshooting MVME1603/mvme1604 boards (continued) condition possible problem try this: .com .com .com .com .com 4 .com u datasheet
gl-1 glossary abbreviations, acronyms, and terms to know this glossary defines some of the abbreviations, acronyms, and key terms used in this document. 10base5 see thick ethernet. 10base2 see thin ethernet. 10baset see twisted-pair ethernet. acia a synchronous c ommunications i nterface a dapter aix a dvanced i nteractive e x ecutive (ibm version of unix) architecture the main overall design in which each individual hardware component of the computer system is interrelated. the most common uses of this term are 8-bit, 16-bit, or 32-bit architectural design systems. ascii a merican s tandard c ode for i nformation i nterchange, a 7-bit code used to encode alphanumeric information. in the ibm- compatible world, this is expanded to 8 bits to encode a total of 256 alphanumeric and control characters. asic a pplication- s pecific i ntegrated c ircuit aui a ttachment u nit i nterface bbram battery backed-up random access memory bi-endian having big-endian and little-endian byte ordering capability. big-endian a byte-ordering method in memory where the address n of a word corresponds to the most significant byte. in an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most significant byte. .com .com .com .com .com 4 .com u datasheet
glossary gl-2 g l o s s a r y bios b asic i nput/ o utput s ystem. the built-in program that controls the basic functions of communications between the processor and the i/o devices (peripherals). also referred to as rom bios. bitblt bit boundary bl ock t ransfer. a type of graphics drawing routine that moves a rectangle of data from one area of display memory to another. the data need not have any particular alignment. blt bl ock t ransfer board the term more commonly used to refer to a pcb (printed circuit board). basically, a flat board made of nonconducting material, such as plastic or fiberglass, on which chips and other electronic components are mounted. also referred to as a circuit board or card. bpi b its p er i nch bps b its p er s econd bus the pathway used to communicate between the cpu, memory, and various input/output devices, including floppy drives and hard disk drives. available in various widths (8-, 16-, and 32-bit), with accompanying increases in speed. cache a high-speed memory that resides logically between a central processing unit (cpu) and the main memory. this temporary memory holds the data and/or instructions that the cpu is most likely to use over and over again and avoids frequent accesses to the slower hard drive or floppy disk drive. cas c olumn a ddress s trobe. the clock signal used in dynamic rams to control the input of column addresses. cd c ompact d isc. a hard, round, flat portable storage unit that stores information digitally. cd-rom c ompact d isk r ead- o nly m emory cfm c ubic f eet per m inute cisc c omplex- i nstruction- s et c omputer. a computer whose processor is designed to sequentially run variable-length instructions, many of which require several clock cycles, that perform complex tasks and thereby simplify programming. .com .com .com .com .com 4 .com u datasheet
glossary gl-3 g l o s s a r y codec co der/ dec oder color difference (cd) the signals of (r-y) and (b-y) without the luminance (-y) signal. the green signals (g-y) can be extracted by these two signals. composite video signal (cvs/cvbs) signal that carries video picture information for color, brightness and synchronizing signals for both horizontal and vertical scans. sometimes referred to as baseband video. cpi c haracters p er i nch cpl c haracters p er l ine cpu c entral p rocessing u nit. the master computer unit in a system. dce d ata c ircuit-terminating e quipment. dll d ynamic l ink l ibrary. a set of functions that are linked to the referencing program at the time it is loaded into memory. dma d irect m emory a ccess. a method by which a device may read or write to memory directly without processor intervention. dma is typically used by block i/o devices. dos d isk o perating s ystem dpi d ots p er i nch dram d ynamic r andom a ccess m emory. a memory technology that is characterized by extremely high density, low power, and low cost. it must be more or less continuously refreshed to avoid loss of data. dte d ata t erminal e quipment. ecc e rror c orrection c ode ecp e xtended c apability p ort eeprom e lectrically e rasable p rogrammable r ead- o nly m emory. a memory storage device that can be written repeatedly with no special erasure fixture. eeproms do not lose their contents when they are powered down. eisa (bus) e xtended i ndustry s tandard a rchitecture (bus) (ibm). an architectural system using a 32-bit bus that allows data to be transferred between peripherals in 32-bit chunks instead of the 16- .com .com .com .com .com 4 .com u datasheet
glossary gl-4 g l o s s a r y bit or 8-bit units that most systems use. with the transfer of larger bits of information, the machine is able to perform much faster than the standard isa bus system. epp e nhanced p arallel p ort eprom e rasable p rogrammable r ead- o nly m emory. a memory storage device that can be written once (per erasure cycle) and read many times. escc e nhanced s erial c ommunication c ontroller esd e lectro- s tatic d ischarge/damage ethernet a local area network standard that uses radio frequency signals carried by coaxial cables. fdc f loppy d isk c ontroller fddi f iber d istributed d ata i nterface. a network based on the use of optical-fiber cable to transmit data in non-return-to-zero, invert- on-1s (nrzi) format at speeds up to 100 mbps. fifo f irst- i n, f irst- o ut. a memory that can temporarily hold data so that the sending device can send data faster than the receiving device can accept it. the sending and receiving devices typically operate asynchronously. firmware the program or specific software instructions that have been more or less permanently burned into an electronic component, such as a rom (read-only memory) or an eprom (erasable programmable read-only memory). frame one complete television picture frame consists of 525 horizontal lines with the ntsc system. one frame consists of two fields. graphics controller on ega and vga, a section of circuitry that can provide hardware assistance for graphics-drawing algorithms by performing logical functions on data written to display memory. hal h ardware a bstraction l ayer. the lower-level hardware interface module of the windows nt operating system. it contains platform-specific functionality. .com .com .com .com .com 4 .com u datasheet
glossary gl-5 g l o s s a r y hardware the term used to describe any of the physical embodiments of a computer system, with emphasis on the electronic circuits (the computer) and electromechanical devices (peripherals) that make up the system. a computing system is normally spoken of as having two major components: hardware and software. hct h ardware c onformance t est. a test used to ensure that both hardware and software conform to the windows nt interface. i/o i nput/ o utput ibc pci/ i sa b ridge c ontroller ide i ntelligent d evice e xpansion ieee i nstitute of e lectrical and e lectronics e ngineers interlaced a graphics system in which the even scanlines are refreshed in one vertical cycle (field), and the odd scanlines are refreshed in another vertical cycle. its advantage is that the video bandwidth is roughly half that required for a non-interlaced system of the same resolution. this results in less costly hardware and may also make it possible to display a resolution that would otherwise be impossible on given hardware. the disadvantage of an interlaced system is flicker, especially when displaying objects that are only a few scanlines high. iq signals similar to the color difference signals (r-y), (b-y) but using different vector axis for encoding or decoding. used by some usa tv and ic manufacturers for color decoding. isa (bus) i ndustry s tandard a rchitecture (bus). the de facto standard system bus for ibm-compatible computers until the introduction of vesa and pci. used in the reference platform specification. (ibm) isasio isa s uper i nput/ o utput device isdn i ntegrated s ervices d igital n etwork. a standard for digitally transmitting video, audio, and electronic data over public phone networks. lan l ocal a rea n etwork led l ight- e mitting d iode lfm l inear f eet per m inute .com .com .com .com .com 4 .com u datasheet
glossary gl-6 g l o s s a r y little-endian a byte-ordering method in memory where the address n of a word corresponds to the least significant byte. in an addressed memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3 being the most significant byte. mblt m ultiplexed bl ock t ransfer mca (bus) m icro c hannel a rchitecture mcg m otorola c omputer g roup mfm m odified f requency m odulation midi m usical i nstrument d igital i nterface. the standard format for recording, storing, and playing digital music. mpc m ultimedia p ersonal c omputer mpc105 the powerpc-to-pci bus bridge chip developed by motorola for the ultra 603/ultra 604 system board. it provides the necessary interface between the mpc603/mpc604 processor and the boot rom (secondary cache), the dram (system memory array), and the pci bus. mpc601 motorolas component designation for the powerpc 601 microprocessor. mpc603 motorolas component designation for the powerpc 603 microprocessor. mpc603 e motorolas component designation for the powerpc 603e microprocessor. mpc604 motorolas component designation for the powerpc 604 microprocessor. mpu m icro p rocessing u nit mtbf m ean t ime b etween f ailures. a statistical term relating to reliability as expressed in power-on hours (poh). it was originally developed for the military and can be calculated several different ways, yielding substantially different results. the specification is based on a large number of samplings in one place, running continuously, and the rate at which failure occurs. mtbf is not representative of how long a device or any individual component is likely to last, nor is it a warranty, but rather an indicator of the relative reliability of a family of products. .com .com .com .com .com 4 .com u datasheet
glossary gl-7 g l o s s a r y multisession the ability to record additional information, such as digitized photographs, on a cd-rom after a prior recording session has ended. non-interlaced a video system in which every pixel is refreshed during every vertical scan. a non-interlaced system is normally more expensive than an interlaced system of the same resolution, and is usually said to have a more pleasing appearance. nonvolatile memory a memory in which the data content is maintained whether the power supply is connected or not. ntsc n ational t elevision s tandards c ommittee (usa) nvram n on- v olatile r andom a ccess m emory oem o riginal e quipment m anufacturer ompac o ver- m olded p ad a rray c arrier os o perating s ystem. the software that manages the computer resources, accesses files, and dispatches programs. otp o ne- t ime p rogrammable palette the range of colors available on the screen, not necessarily simultaneously. for vga, this is either 16 or 256 simultaneous colors out of 262,144. parallel port a connector that can exchange data with an i/o device eight bits at a time. this port is more commonly used for the connection of a printer to a system. pci (local bus) p eripheral c omponent i nterconnect (local bus) (intel). a high- performance, 32-bit internal interconnect bus used for data transfer to peripheral controller components, such as those for audio, video, and graphics. pcmcia (bus) p ersonal c omputer m emory c ard i nternational a ssociation (bus). a standard external interconnect bus which allows peripherals adhering to the standard to be plugged in and used without further system modification. pds p rocessor d irect s lot physical address a binary address that refers to the actual location of information stored in secondary storage. pib p ci-to- i sa b ridge .com .com .com .com .com 4 .com u datasheet
glossary gl-8 g l o s s a r y pixel an acronym for picture element, also called a pel. a pixel is the smallest addressable graphic on a display screen. in rgb systems, the color of a pixel is defined by some red intensity, some green intensity, and some blue intensity. pll p hase- l ocked l oop pmc p ci m ezzanine c ard power p erformance o ptimized w ith e nhanced r isc architecture (ibm) powerpc? the trademark used to describe the p erformance o ptimized w ith e nhanced r isc microprocessor architecture for p ersonal c omputers developed by the ibm corporation. powerpc is superscalar, which means it can handle more than one instruction per clock cycle. instructions can be sent simultaneously to three types of independent execution units (branch units, fixed-point units, and floating-point units), where they can execute concurrently, but finish out of order. powerpc is used by motorola, inc. under license from ibm. powerpc 601? the first implementation of the powerpc family of microprocessors. this cpu incorporates a memory management unit with a 256-entry buffer and a 32kb unified (instruction and data) cache. it provides a 64-bit data bus and a separate 32-bit address bus. powerpc 601 is used by motorola, inc. under license from ibm. powerpc 603? the second implementation of the powerpc family of microprocessors. this cpu incorporates a memory management unit with a 64-entry buffer and an 8kb (instruction and data) cache. it provides a selectable 32-bit or 64-bit data bus and a separate 32-bit address bus. powerpc 603 is used by motorola, inc. under license from ibm. powerpc 603e? a variant of the second implementation of the powerpc family of microprocessors. this cpu incorporates a faster clock (100mhz) and 256kb l2 cache. powerpc 603e is used by motorola, inc. under license from ibm. powerpc 604? the third implementation of the powerpc family of microprocessors currently under development. powerpc 604 is used by motorola, inc. under license from ibm. .com .com .com .com .com 4 .com u datasheet
glossary gl-9 g l o s s a r y powerpc reference platform (prp) a specification published by the ibm power personal systems division which defines the devices, interfaces, and data formats that make up a prp-compliant system using a powerpc processor. powerstack? risc pc (system board) a powerpc-based computer board platform developed by the motorola computer group. it supports microsofts windows nt and ibms aix operating systems. prp see powerpc reference platform (prp). prp-compliant see powerpc reference platform (prp). prp spec see powerpc reference platform (prp). prom p rogrammable r ead- o nly m emory ps/2 p ersonal s ystem/ 2 (ibm) qfp q uad f lat p ackage ram r andom- a ccess m emory. the temporary memory that a computer uses to hold the instructions and data currently being worked with. all data in ram is lost when the computer is turned off. ras r ow a ddress s trobe. a clock signal used in dynamic rams to control the input of the row addresses. reduced-instruction-set computer (risc) a computer in which the processors instruction set is limited to constant-length instructions that can usually be executed in a single clock cycle. rfi r adio f requency i nterference rgb the three separate color signals: r ed, g reen, and b lue. used with color displays, an interface that uses these three color signals as opposed to an interface used with a monochrome display that requires only a single signal. both digital and analog rgb interfaces exist. risc see reduced-instruction-set computer (risc). rom r ead- o nly m emory rtc r eal- t ime c lock sbc s ingle b oard c omputer .com .com .com .com .com 4 .com u datasheet
glossary gl-10 g l o s s a r y scsi s mall c omputer s ystems i nterface. an industry-standard high- speed interface primarily used for secondary storage. the scsi-1 implementation provides up to 5 mbps data transfer. scsi-2 (fast/wide) an improvement over plain scsi; and includes command queuing. fast scsi provides 10 mbps data transfer on an 8-bit bus. wide scsi provides up to 40 mbps data transfer on a 16- or 32-bit bus. serial port a connector that can exchange data with an i/o device one bit at a time. it may operate synchronously or asynchronously, and may include start bits, stop bits, and/or parity. sim s erial i nterface m odule simm s ingle i nline m emory m odule. a small circuit board with ram chips (normally surface mounted) that is designed to fit into a standard slot. sio s uper i/o controller smp s ymmetric m ulti p rocessing. a computer architecture in which tasks are distributed among two or more local processors. smt s urface m ount t echnology. a method of mounting devices (such as integrated circuits, resistors, capacitors, and others) on a printed circuit board, characterized by not requiring mounting holes. rather, the devices are soldered to pads on the printed circuit board. surface-mount devices are typically smaller than the equivalent through-hole devices. software the term used to describe any single program or group of programs, languages, operating procedures, and documentation of a computer system. a computing system is normally spoken of as having two major components: hardware and software. software is the real interface between the user and the computer. sram s tatic r andom a ccess m emory ssblt s ource s ynchronous bl ock t ransfer standard(s) a set of detailed technical guidelines used as a means of establishing uniformity in an area of hardware or software development. .com .com .com .com .com 4 .com u datasheet
glossary gl-11 g l o s s a r y svga s uper v ideo g raphics a rray (ibm). an improved vga monitor standard that provides at least 256 simultaneous colors and a screen resolution of 800 x 600 pixels. teletext one-way broadcast of digital information. the digital information is injected in the broadcast tv signal, vbi, or full field, the transmission medium could be satellite, microwave, cable, etc. the display medium is a regular tv receiver. thick ethernet (10base5) an ethernet implementation in which the physical medium is a double-shielded, 50-ohm coaxial cable capable of carrying data at 10 mbps for a length of 500 meters (also referred to as thicknet). thin ethernet (10base2) an ethernet implementation in which the physical medium is a single-shielded, 50-ohm rg58a/u coaxial cable capable of carrying data at 10 mbps for a length of 185 meters (also referred to as aui or thinnet). twisted-pair ethernet (10baset) an ethernet implementation in which the physical medium is an unshielded pair of entwined wires capable of carrying data at 10 mbps for a maximum distance of 185 meters. uart u niversal a synchronous r eceiver/ t ransmitter uv u ltra v iolet uvga u ltra v ideo g raphics a rray. an improved vga monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels. vertical blanking interval (vbi) the time it takes the beam to fly back to the top of the screen in order to retrace the opposite field (odd or even). vbi is on the order of 20 tv lines. teletext information is transmitted over 4 of these lines (lines 14-17). vesa (bus) v ideo e lectronics s tandards a ssociation (or vl bus). an internal interconnect standard for transferring video information to a computer display system. .com .com .com .com .com 4 .com u datasheet
glossary gl-12 g l o s s a r y vga v ideo g raphics a rray (ibm). the third and most common monitor standard used today. it provides up to 256 simultaneous colors and a screen resolution of 640 x 480 pixels. virtual address a binary address issued by a cpu that indirectly refers to the location of information in primary memory, such as main memory. when data is copied from disk to main memory, the physical address is changed to the virtual address. vl bus see v esa l ocal bus (vl bus). vmechip2 mcg second generation vmebus interface asic (motorola) vme2pci mcg asic that interfaces between the pci bus and the vmechip2 device. volatile memory a memory in which the data content is lost when the power supply is disconnected. vram v ideo (dynamic) r andom a ccess m emory. memory chips with two ports, one used for random accesses and the other capable of serial accesses. once the serial port has been initialized (with a transfer cycle), it can operate independently of the random port. this frees the random port for cpu accesses. the result of adding the serial port is a significantly reduced amount of interference from screen refresh. vrams cost more per bit than drams. windows nt? the trademark representing windows n ew t echnology, a computer operating system developed by the microsoft corporation. xga e x tended g raphics a rray. an improved ibm vga monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels. y signal luminance. parameter that determines the brightness (but not the color) of each spot (pixel) on a crt screen in color or b/w systems. .com .com .com .com .com 4 .com u datasheet
in-1 index a abort (interrupt) signal 2-23, 3-16, 3-19 access time-out 6-19 times 3-26 ambient air temperature b-2 assembly language 5-2 autoboot enable 6-6 b backplane jumpers 1-39 base board(s) differences 1-1 layout 1-7, 1-18 block diagram MVME1603/mvme1604 3-4 board 3-16 configuration 1-6 configuration register 3-16 placement 1-38 information block 6-2 structure 6-2 c cables b-2 cnfg 6-2 commands 5-3 debugger 5-4 conductive chassis rails b-3 configure ppc1bug parameters 6-3 vmebus interface 6-12 configure board information block 6-2 connector pin assignments 4-1 console port selection 1-8, 1-24 control/status registers 1-46 cooling requirements b-2 counters 3-14 d data circuit-terminating equipment (dce) c-3 data terminal equipment (dte) c-3 dce 3-16 debugger commands 5-4 firmware (ppcbug) 5-1, 6-1 decimal number 4 diagnostics 5-1 test groups 5-7 disk drive connector 4-15 controller 3-10, 3-12, c-1 dma channels 2-24 dram base address 1-45 speed 6-10 dte 3-16 e eia-232-d interconnections c-3 eia-530 interconnections c-6 interface characteristics c-8 .com .com .com .com .com 4 .com u datasheet
index in-2 computer group literature center web site i n d e x endian issues 2-25 53c825 or 53c810(scsi) 2-28 big-endian mode 2-26 gd5434 (graphics) 2-28 little-endian mode 2-27 mpc105 function 2-25 pci domain 2-28 processor/memory domain 2-25 vme2pci function 2-28 vmebus domain 2-28 env command 6-3 environmental parameters 6-1 esd precautions 1-32 ethernet address 3-7 ethernet (see 82596ca and lan) 1-46, 3-22 ethernet transceiver interface 1-47, 3-23 power 1-47 power distribution 3-23 f features hardware 3-1 isa super i/o device 3-10 vmechip2 3-10 first access length (romfal) 3-26 flash device speed 3-26 forced air cooling b-2 f-page address decoder 6-18 front panel controls 2-1, 3-21 functional description 3-25 fuses 3-16, 3-22, 3-23 mvme1600-001 base board 1-46 mvme1600-011 base board 1-47 g general-purpose readable jumpers mvme1600-001 base board 1-8, 1-23 global bus timeout 1-45 graphics (gd5434) 2-28 graphics interface 3-8 ground connections c-9 h hexadecimal character 4 i ibc arbiter configuration diagram 2-19 dma channel assignments 2-24 interrupt handler block diagram 2-22 installation considerations 1-45 mvme712m transition module 1-42 mvme760 transition module 1-39 pm603/pm604 mezzanine 1-33 ram104 mezzanine 1-35 vmemodule assembly 1-38 interconnect signals 4-1 interconnections, serial c-3, c-6 interrupt support 2-20 isa bridge controller functions 3-13 j jumper headers mvme1600-001 base board 1-7 mvme1600-011 base board 1-18 mvme712m transition module 1-29 mvme760 transition module 1-15 k keyboaard/mouse interface 3-10 .com .com .com .com .com 4 .com u datasheet
http://www.mcg.mot.com/literature in-3 i n d e x l l2 cache 1-1, 3-1, 3-3, 4-6 lan transceiver 1-46, 3-22 last access length (romnal) 3-26 lcp2 adapter board 3-7 local reset (lrst) 2-2, 3-19 lowercase 5-8 m machine check interrupt (mcp_) 2-21 manual terminology 4 manufacturers documents a-2 maskable interrupts 2-21 master address decoders 6-15 enable 6-15 mcp_ (machine check interrupt) 2-21 memory map(s) 2-4 isa/pci i/o 2-7 local i/o 2-6 overall 2-5 pci local bus 2-9 vme2pci 2-10 memory size 6-10 mezzanine modules 1-1 minimum romfal and romnal values 3-26 module id (syn/async ports) 3-16 multiplexing function (p2) 3-16, 3-18 MVME1603/mvme1604 interrupt architecture 2-20 n netboot enable 6-8 network auto boot enable 6-8 non-volatile ram (nvram) 6-1, 6-3 normal address range 2-4 o operating parameters 6-1 p p2 adapter board 3-7, 3-28 multiplexing function 3-16, 3-18 parallel port 3-10 pci arbitration assignments 2-19 bus 3-4, 3-9 pin assignments, connector 4-1 power distribution 3-22 ppcbug debugger firmware 5-1, 6-1 r real-time clock 3-13 related specifications a-7 remote control/status connector 3-14 mvme1600-011 base board 1-47 remote panel interface 3-23 remote status/control connector 3-24 mvme1600-001 base board 1-13 mvme1600-011 base board 1-25 required equipment 1-2 resetting the system 2-2, 3-20 restart mode 5-8 rf emissions b-3 romboot enable 6-7, 6-11 romfal 6-10 romfal/romnal values 3-26 romnal 6-11 s scsi (53c825 or 53c810) 2-28 bus 6-5 interface 3-6 termination 3-7, 3-16 terminator power 1-46, 1-47, 3-23, 3-22 serial communications interface 3-15, c-2 serial interface modules (sims) 3-27 parameters c-4 serial ports 3-10, 3-15 .com .com .com .com .com 4 .com u datasheet
index in-4 computer group literature center web site i n d e x set environment to bug/operating system (env) 6-3 shielded cables (see also cables) b-2 short i/o address decoder 6-18 slave address decoders 6-13 enable 6-14 sources of reset 2-24 speaker output 1-47, 3-14, 3-24 specifications, base board b-1 sysfail* 6-5 system controller 1-38 reset (srst) 3-19 t time-out 6-19 timers 3-14 transition modules 1-2, 1-47, 3-23, 3-27 installation 1-38 transmitters eia-232-d c-5 eia-530 c-8 u uppercase 5-8 user-definable jumpers 1-8, 1-24 v vga port 3-8 video port 1-9 vme2pci 6-3, 6-12 vmebus address/data configurations 1-45 interface 6-12 time-out 6-19 vmechip2 6-3, 6-12, 6-18 .com .com .com .com .com 4 .com u datasheet
? ? ? ? ? ? ? ? MVME1603/mvme1604 single board computer installation and use MVME1603/mvme1604 single board computer installation and use 34 pages 1/8 spine 36 - 84 pages 3/16 & 1/4 spine 86 - 100 pages 5/16 spine 102 - 180 pages 3/8 - 1/2 spine 182 - 308 pages 5/8 - 1 1/8 spine 2 lines allowed cover .com .com .com .com .com 4 .com u datasheet
.com .com .com .com 4 .com u datasheet

▲Up To Search▲

Price & Availability of MVME1603

	To Download MVME1603 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .